#define RTC_CCR_CLKEN   (0x00000001)#define RTC_CCR_CTCRST  (0x00000002)#define RTC_CCR_TEST    (0x0000000c)#define RTC_CCR_CLKSRC  (0x00000010)#define RTC_CIIR_IMSEC  (0x00000001)#define RTC_CIIR_IMMIN  (0x00000002)#define RTC_CIIR_IMHOUR (0x00000004)#define RTC_CIIR_IMDOM  (0x00000008)#define RTC_CIIR_IMDOW  (0x00000010)#define RTC_CIIR_IMDOY  (0x00000020)#define RTC_CIIR_IMMON  (0x00000040)#define RTC_CIIR_IMYEAR (0x00000080)#define RTC_CIIR_IMMASK (0x000000ff)#define RTC_AMR_AMRSEC  (0x00000001)#define RTC_AMR_AMRMIN  (0x00000002)#define RTC_AMR_AMRHOUR (0x00000004)#define RTC_AMR_AMRDOM  (0x00000008)#define RTC_AMR_AMRDOW  (0x00000010)#define RTC_AMR_AMRDOY  (0x00000020)#define RTC_AMR_AMRMON  (0x00000040)#define RTC_AMR_AMRYEAR (0x00000080)#define RTC_AMR_AMRMASK (0x000000ff)typedef struct __attribute__ ((packed)) {  union  {    struct    {      unsigned int counter   : 14;      unsigned int rsvd15_31 : 18;    };    unsigned int i;  };}rtcCTC_t;typedef struct __attribute__ ((packed)) {  union  {    struct     {      unsigned int seconds   : 6;      unsigned int rsvd7_6   : 2;      unsigned int minutes   : 6;      unsigned int rsvd14_15 : 2;      unsigned int hours     : 5;      unsigned int rsvd21_23 : 3;      unsigned int dow       : 3;      unsigned int rsvd27_31 : 5;    };    unsigned int i;  };}rtcCTIME0_t;typedef struct __attribute__ ((packed)) {  union  {    struct    {      unsigned int dom       : 5;      unsigned int rsvd5_7   : 3;      unsigned int month     : 4;      unsigned int rsvd12_15 : 4;      unsigned int year      : 12;      unsigned int rsvd28_31 : 4;    };    unsigned int i;  };}rtcCTIME1_t;typedef struct __attribute__ ((packed)) {  union  {    struct     {      unsigned int doy       : 12;      unsigned int rsvd12_31 : 20;    };    unsigned int i;  };}rtcCTIME2_t;/*################################################################################ WD - Watchdog##############################################################################*/#define WD_MOD        (*(pREG32 (0xe0000000)))#define WD_TC         (*(pREG32 (0xe0000004)))#define WD_FEED       (*(pREG32 (0xe0000008)))#define WD_TV         (*(pREG32 (0xe000000c)))#define WD_MOD_WDEN   (0x00000001)#define WD_MOD_RESET  (0x00000002)#define WD_MOD_TOF    (0x00000004)#define WD_MOD_INT    (0x00000008)#define WD_MOD_MASK   (0x0000000f)#define WD_FEED_FEED1 (0x000000aa)#define WD_FEED_FEED2 (0x00000055)/*################################################################################ System Control Block##############################################################################*/#define SCB_MEMMAP          (*(pREG32 (0xe01fc040)))#define SCB_PLLCON          (*(pREG32 (0xe01fc080)))#define SCB_PLLCFG          (*(pREG32 (0xe01fc084)))#define SCB_PLLSTAT         (*(pREG32 (0xe01fc088)))#define SCB_PLLFEED         (*(pREG32 (0xe01fc08c)))#define SCB_PCON            (*(pREG32 (0xe01fc0c0)))#define SCB_PCONP           (*(pREG32 (0xe01fc0c4)))#define SCB_VPBDIV          (*(pREG32 (0xe01fc100)))#define SCB_EXTINT          (*(pREG32 (0xe01fc140)))#define SCB_INTWAKE         (*(pREG32 (0xe01fc144)))#define SCB_EXTMODE         (*(pREG32 (0xe01fc148)))#define SCB_EXTPOLAR        (*(pREG32 (0xe01fc14c)))#define SCB_RSIR            (*(pREG32 (0xe01fc180)))#define SCB_CSPR            (*(pREG32 (0xe01fc184)))#define SCB_SCS             (*(pREG32 (0xe01fc1a0)))#define SCB_MEMMAP_BLM      (0x00000000)#define SCB_MEMMAP_UFL      (0x00000001)#define SCB_MEMMAP_URM      (0x00000002)#define SCB_MEMMAP_RSVD     (0x00000003)#define SCB_MEMMAP_MASK     (0x00000003)#define SCB_PLLCON_PLLE     (0x00000001)#define SCB_PLLCON_PLLC     (0x00000002)#define SCB_PLLCON_MASK     (0x00000003)#define SCB_PLLCFG_MSEL     (0x0000001f)#define SCB_PLLCFG_PSEL     (0x00000060)#define SCB_PLLCFG_MUL1     (0x00000000)#define SCB_PLLCFG_MUL2     (0x00000001)#define SCB_PLLCFG_MUL3     (0x00000002)#define SCB_PLLCFG_MUL4     (0x00000003)#define SCB_PLLCFG_MUL5     (0x00000004)#define SCB_PLLCFG_MUL6     (0x00000005)#define SCB_PLLCFG_MUL7     (0x00000006)#define SCB_PLLCFG_MUL8     (0x00000007)#define SCB_PLLCFG_MUL9     (0x00000008)#define SCB_PLLCFG_MUL10    (0x00000009)#define SCB_PLLCFG_MUL11    (0x0000000a)#define SCB_PLLCFG_MUL12    (0x0000000b)#define SCB_PLLCFG_MUL13    (0x0000000c)#define SCB_PLLCFG_MUL14    (0x0000000d)#define SCB_PLLCFG_MUL15    (0x0000000e)#define SCB_PLLCFG_MUL16    (0x0000000f)#define SCB_PLLCFG_MUL17    (0x00000010)#define SCB_PLLCFG_MUL18    (0x00000011)#define SCB_PLLCFG_MUL19    (0x00000012)#define SCB_PLLCFG_MUL20    (0x00000013)#define SCB_PLLCFG_MUL21    (0x00000014)#define SCB_PLLCFG_MUL22    (0x00000015)#define SCB_PLLCFG_MUL23    (0x00000016)#define SCB_PLLCFG_MUL24    (0x00000017)#define SCB_PLLCFG_MUL25    (0x00000018)#define SCB_PLLCFG_MUL26    (0x00000019)#define SCB_PLLCFG_MUL27    (0x0000001a)#define SCB_PLLCFG_MUL28    (0x0000001b)#define SCB_PLLCFG_MUL29    (0x0000001c)#define SCB_PLLCFG_MUL30    (0x0000001d)#define SCB_PLLCFG_MUL31    (0x0000001e)#define SCB_PLLCFG_MUL32    (0x0000001f)#define SCB_PLLCFG_DIV1     (0x00000000)#define SCB_PLLCFG_DIV2     (0x00000020)#define SCB_PLLCFG_DIV4     (0x00000040)#define SCB_PLLCFG_DIV8     (0x00000060)#define SCB_PLLCFG_MASK     (0x0000007f)#define SCB_PLLSTAT_MSEL    (0x0000001f)#define SCB_PLLSTAT_PSEL    (0x00000060)#define SCB_PLLSTAT_PLLE    (0x00000100)#define SCB_PLLSTAT_PLLC    (0x00000200)#define SCB_PLLSTAT_PLOCK   (0x00000400)#define SCB_PLLFEED_FEED1   (0x000000aa)#define SCB_PLLFEED_FEED2   (0x00000055)#define SCB_PCON_IDL        (0x00000001)#define SCB_PCON_PD         (0x00000002)#define SCB_PCON_PDBOD      (0x00000004)#define SCB_PCON_BODPDM     (0x00000008)#define SCB_PCON_BOGD       (0x00000010)#define SCB_PCON_BORD       (0x00000020)#define SCB_PCON_MASK       (0x0000003f)#define SCB_PCONP_ALLOFF    (0x00000000)#define SCB_PCONP_PCTIM0    (0x00000002)#define SCB_PCONP_PCTIM1    (0x00000004)#define SCB_PCONP_PCUART0   (0x00000008)#define SCB_PCONP_PCUART1   (0x00000010)#define SCB_PCONP_PCPWM0    (0x00000020)#define SCB_PCONP_PCI2C0    (0x00000080)#define SCB_PCONP_PCSPI0    (0x00000100)#define SCB_PCONP_PCRTC     (0x00000200)#define SCB_PCONP_PCSPI1    (0x00000400)#define SCB_PCONP_PCAD0     (0x00001000)#define SCB_PCONP_PCI2C1    (0x00080000)#define SCB_PCONP_PCAD1     (0x00100000)#define SCB_PCONP_PUSB      (0x80000000)#define SCB_PCONP_ATRESET   (0x000003be)#define SCB_PCONP_MASK      (0x801817be)#define SCB_VPBDIV_25       (0x00000000)#define SCB_VPBDIV_100      (0x00000001)#define SCB_VPBDIV_50       (0x00000002)#define SCB_VPBDIV_RSVD     (0x00000003)#define SCB_VPBDIV_MASK     (0x00000003)#define SCB_EXTINT_EINT0    (0x00000001)#define SCB_EXTINT_EINT1    (0x00000002)#define SCB_EXTINT_EINT2    (0x00000004)#define SCB_EXTINT_EINT3    (0x00000008)#define SCB_EXTINT_MASK     (0x0000000f)#define SCB_INTWAKE_EINT0   (0x00000001)#define SCB_INTWAKE_EINT1   (0x00000002)#define SCB_INTWAKE_EINT2   (0x00000004)#define SCB_INTWAKE_EINT3   (0x00000008)#define SCB_INTWAKE_USB     (0x00000020)#define SCB_INTWAKE_BOD     (0x00004000)#define SCB_INTWAKE_RTC     (0x00008000)#define SCB_INTWAKE_MASK    (0x0000c02f)#define SCB_EXTMODE_EINT0   (0x00000001)#define SCB_EXTMODE_EINT1   (0x00000002)#define SCB_EXTMODE_EINT2   (0x00000004)#define SCB_EXTMODE_EINT3   (0x00000008)#define SCB_EXTMODE_MASK    (0x0000000f)#define SCB_EXTPOLAR_EINT0  (0x00000001)#define SCB_EXTPOLAR_EINT1  (0x00000002)#define SCB_EXTPOLAR_EINT2  (0x00000004)#define SCB_EXTPOLAR_EINT3  (0x00000008)#define SCB_EXTPOLAR_MASK   (0x0000000f)#define SCB_RSIR_POR        (0x00000001)#define SCB_RSIR_EXTR       (0x00000002)#define SCB_RSIR_WDTR       (0x00000004)#define SCB_RSIR_BODR       (0x00000008)#define SCB_RSIR_MASK       (0x0000000f)#define SCB_SCS_GPIO0M      (0x00000001)#define SCB_SCS_GPIO1M      (0x00000002)#define SCB_SCS_MASK        (0x00000003)/*################################################################################ System Control Block (USB)##############################################################################*/#define USB_PLLCON                (*(pREG32 (0xe01fc0a0)))#define USB_PLLCFG                (*(pREG32 (0xe01fc0a4)))#define USB_PLLSTAT               (*(pREG32 (0xe01fc0a8)))#define USB_PLLFEED               (*(pREG32 (0xe01fc0ac)))#define USB_IntSt                 (*(pREG32 (0xe01fc1c0)))#define USB_DevIntSt              (*(pREG32 (0xe0090000)))#define USB_DevIntEn              (*(pREG32 (0xe0090004)))#define USB_DevIntClr             (*(pREG32 (0xe0090008)))#define USB_DevIntSet             (*(pREG32 (0xe009000c)))#define USB_DevIntPri             (*(pREG32 (0xe009002c)))#define USB_EpIntSt               (*(pREG32 (0xe0090030)))#define USB_EpIntEn               (*(pREG32 (0xe0090034)))#define USB_EpIntClr              (*(pREG32 (0xe0090038)))#define USB_EpIntSet              (*(pREG32 (0xe009003c)))#define USB_EpIntPri              (*(pREG32 (0xe0090040)))#define USB_ReEP                  (*(pREG32 (0xe0090044)))#define USB_EpInd                 (*(pREG32 (0xe0090048)))#define USB_MaxPSize              (*(pREG32 (0xe009004c)))#define USB_RxData                (*(pREG32 (0xe0090018)))#define USB_RxPLen                (*(pREG32 (0xe0090020)))#define USB_TxData                (*(pREG32 (0xe009001c)))#define USB_TxPLen                (*(pREG32 (0xe0090024)))#define USB_Ctrl                  (*(pREG32 (0xe0090028)))#define USB_CmdCode               (*(pREG32 (0xe0090010)))#define USB_CmdData               (*(pREG32 (0xe0090014)))#define USB_DMARSt                (*(pREG32 (0xe0090050)))#define USB_DMARClr               (*(pREG32 (0xe0090054)))#define USB_DMARSet               (*(pREG32 (0xe0090058)))#define USB_UDCAH                 (*(pREG32 (0xe0090080)))#define USB_EpDMASt               (*(pREG32 (0xe0090084)))#define USB_EpDMAEn               (*(pREG32 (0xe0090088)))#define USB_EpDMADis              (*(pREG32 (0xe009008c)))#define USB_DMAIntSt              (*(pREG32 (0xe0090090)))#define USB_DMAIntEn              (*(pREG32 (0xe0090094)))#define USB_Eo