{ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},  /* ARM Instructions.  */  {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},  {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},  {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},  {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},  {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},  {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},  {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},  {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},  {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},  {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},  {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},  {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},  {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},  {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},  {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},  {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},  {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},  {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},  {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},  {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},  /* The rest.  */  {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},  {0, 0x00000000, 0x00000000, 0}};/* print_insn_thumb16 recognizes the following format control codes:   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)   %<bitfield>I         print bitfield as a signed decimal   				(top bit of range being the sign bit)   %N                   print Thumb register mask (with LR)   %O                   print Thumb register mask (with PC)   %M                   print Thumb register mask   %b			print CZB's 6-bit unsigned branch destination   %s			print Thumb right-shift immediate (6..10; 0 == 32).   %<bitfield>r		print bitfield as an ARM register   %<bitfield>d		print bitfield as a decimal   %<bitfield>H         print (bitfield * 2) as a decimal   %<bitfield>W         print (bitfield * 4) as a decimal   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol   %<bitfield>B         print Thumb branch destination (signed displacement)   %<bitfield>c         print bitfield as a condition code   %<bitnum>'c		print specified char iff bit is one   %<bitnum>?ab		print a if bit is one else print b.  */static const struct opcode16 thumb_opcodes[] ={  /* Thumb instructions.  */  /* ARM V6K no-argument instructions.  */  {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},  {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},  {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},  {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},  {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},  {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"},  /* ARM V6T2 instructions.  */  {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b"},  {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b"},  {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"},  {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"},  {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"},  {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"},  {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"},  {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"},  {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"},  /* ARM V6.  */  {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},  {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},  {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble"},  {ARM_EXT_V6, 0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},  {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},  /* ARM V5 ISA extends Thumb.  */  {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"},  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */  {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"},	/* note: 4 bit register number.  */  /* ARM V4T ISA (Thumb v1).  */  {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},  /* Format 4.  */  {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"},  {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"},  /* format 13 */  {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"},  {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"},  /* format 5 */  {ARM_EXT_V4T, 0x4700, 0xFF80, "bx\t%S"},  {ARM_EXT_V4T, 0x4400, 0xFF00, "add\t%D, %S"},  {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp\t%D, %S"},  {ARM_EXT_V4T, 0x4600, 0xFF00, "mov\t%D, %S"},  /* format 14 */  {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"},  {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},  /* format 2 */  {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},  {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},  {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},  {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},  /* format 8 */  {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},  {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},  {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},  /* format 7 */  {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},  {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},  /* format 1 */  {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"},  {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"},  {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"},  /* format 3 */  {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"},  {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},  {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"},  {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"},  /* format 6 */  {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */  /* format 9 */  {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},  {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},  {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},  {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},  /* format 10 */  {ARM_EXT_V4T, 0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},  {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},  /* format 11 */  {ARM_EXT_V4T, 0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},  {ARM_EXT_V4T, 0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},  /* format 12 */  {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},  {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},  /* format 15 */  {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"},  {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"},  /* format 17 */  {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc\t%0-7d"},  /* format 16 */  {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"},  /* format 18 */  {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"},  /* The E800 .. FFFF range is unconditionally redirected to the     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs     are processed via that table.  Thus, we can never encounter a     bare "second half of BL/BLX(1)" instruction here.  */  {ARM_EXT_V1,  0x0000, 0x0000, "undefined"},  {0, 0, 0, 0}};/* Thumb32 opcodes use the same table structure as the ARM opcodes.   We adopt the convention that hw1 is the high 16 bits of .value and   .mask, hw2 the low 16 bits.   print_insn_thumb32 recognizes the following format control codes:       %%		%       %I		print a 12-bit immediate from hw1[10],hw2[14:12,7:0]       %M		print a modified 12-bit immediate (same location)       %J		print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]       %K		print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]       %S		print a possibly-shifted Rm       %a		print the address of a plain load/store       %w		print the width and signedness of a core load/store       %m		print register mask for ldm/stm       %E		print the lsb and width fields of a bfc/bfi instruction       %F		print the lsb and width fields of a sbfx/ubfx instruction       %b		print a conditional branch offset       %B		print an unconditional branch offset       %s		print the shift field of an SSAT instruction       %R		print the rotation field of an SXT instruction