--為了顯示效果更佳，將時(shí)鐘適當(dāng)分頻；此模塊可不用
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fenpin is
	port(
		clk:in std_logic;
		fenpin:out std_logic
		);
end fenpin;
architecture fenpin of fenpin is
signal clk1:std_logic_vector(3 downto 0);
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			clk1<=clk1+1;
		end if;
		fenpin<=clk;
	end process;
end fenpin;