module Main(clk_in,rst,in1,in2,in3,in4,out,FSK_out,wrong);
//,clk_DATA);//,psk_rst,count);

	input clk_in,rst,in1,in2,in3,in4;
	output out,wrong;	//result
	output FSK_out;		//observer
	//output clk_DATA,psk_rst;	//temp
	//output [4:0] count;	//temp
	wire clk_DATA,DATA_in;
	wire DATA_out;
	
	clkgen(.clk_in(clk_in),.clk_DATA(clk_DATA));
	encode(.clk(clk_DATA),.out(DATA_in),.in1(in1),.in2(in2),.in3(in3),.in4(in4));
	FSK_mod(.clk_in(clk_in),.rst(rst),.DATA(DATA_in),.FSK_out(FSK_out));
	FSK_demod(.clk_in(clk_in),.clk_DATA(clk_DATA),.FSK_receive(FSK_out),.DATA(DATA_out));
				//,.psk_rst(psk_rst),.count(count));
	
	decode1(.clk(clk_DATA),.clr(rst),.in(DATA_out),.out(out),.wrong(wrong));
	
	
endmodule