Assembler report for vga_dis
Fri Jan 02 22:37:21 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
  5. Assembler Device Options: E:/個人項目/BJ-EPM240學習板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.pof
  6. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Fri Jan 02 22:37:21 2009 ;
; Revision Name         ; vga_dis                               ;
; Top-level Entity Name ; vga_dis                               ;
; Family                ; MAX II                                ;
; Device                ; EPM240T100C5                          ;
+-----------------------+---------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                         ;
+--------------------------------------------------------------------------------+-----------+---------------+
; Option                                                                         ; Setting   ; Default Value ;
+--------------------------------------------------------------------------------+-----------+---------------+
; Generate Serial Vector Format File (.svf) for Target Device                    ; Off       ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                    ; Off       ; Off           ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device    ; On        ; On            ;
; In-System Programming Default Clamp State                                      ; Tri-state ; Tri-state     ;
; Compression mode                                                               ; Off       ; Off           ;
; Clock source for configuration device                                          ; Internal  ; Internal      ;
; Clock frequency of the configuration device                                    ; 10 MHZ    ; 10 MHz        ;
; Divide clock frequency by                                                      ; 1         ; 1             ;
; JTAG user code for target device                                               ; Ffffffff  ; Ffffffff      ;
; Auto user code                                                                 ; Off       ; Off           ;
; Security bit                                                                   ; Off       ; Off           ;
; Configuration device                                                           ; Auto      ; Auto          ;
; JTAG user code for configuration device                                        ; Ffffffff  ; Ffffffff      ;
; Configuration device auto user code                                            ; Off       ; Off           ;
; Generate Tabular Text File (.ttf) For Target Device                            ; Off       ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                              ; Off       ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device    ; Off       ; Off           ;
; Hexadecimal Output File start address                                          ; 0         ; 0             ;
; Hexadecimal Output File count direction                                        ; Up        ; Up            ;
; Use smart compilation                                                          ; Off       ; Off           ;
+--------------------------------------------------------------------------------+-----------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Assembler Generated Files                                                                             ;
+-------------------------------------------------------------------------------------------------------+
; File Name                                                                                             ;
+-------------------------------------------------------------------------------------------------------+
; E:/個人項目/BJ-EPM240學習板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.pof ;
+-------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: E:/個人項目/BJ-EPM240學習板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.pof ;
+----------------+----------------------------------------------------------------------------------------------------------------+
; Option         ; Setting                                                                                                        ;
+----------------+----------------------------------------------------------------------------------------------------------------+
; Device         ; EPM240T100C5                                                                                                   ;
; JTAG usercode  ; 0xFFFFFFFF                                                                                                     ;
; Checksum       ; 0x00180C88                                                                                                     ;
+----------------+----------------------------------------------------------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jan 02 22:37:16 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga_dis -c vga_dis
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Fri Jan 02 22:37:21 2009
    Info: Elapsed time: 00:00:05