{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 27 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register x_cnt\[10\] register y_cnt\[9\] 109.25 MHz 9.153 ns Internal " "Info: Clock \"clk\" has Internal fmax of 109.25 MHz between source register \"x_cnt\[10\]\" and destination register \"y_cnt\[9\]\" (period= 9.153 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.444 ns + Longest register register " "Info: + Longest register to register delay is 8.444 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x_cnt\[10\] 1 REG LC_X5_Y4_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'x_cnt\[10\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { x_cnt[10] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.328 ns) + CELL(0.740 ns) 2.068 ns Equal0~66 2 COMB LC_X5_Y4_N6 1 " "Info: 2: + IC(1.328 ns) + CELL(0.740 ns) = 2.068 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'Equal0~66'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.068 ns" { x_cnt[10] Equal0~66 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.914 ns) 3.698 ns Equal0~67 3 COMB LC_X5_Y4_N1 5 " "Info: 3: + IC(0.716 ns) + CELL(0.914 ns) = 3.698 ns; Loc. = LC_X5_Y4_N1; Fanout = 5; COMB Node = 'Equal0~67'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.630 ns" { Equal0~66 Equal0~67 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.747 ns) 6.447 ns y_cnt\[0\]~165 4 COMB LC_X5_Y2_N0 2 " "Info: 4: + IC(2.002 ns) + CELL(0.747 ns) = 6.447 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; COMB Node = 'y_cnt\[0\]~165'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.749 ns" { Equal0~67 y_cnt[0]~165 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.570 ns y_cnt\[1\]~166 5 COMB LC_X5_Y2_N1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 6.570 ns; Loc. = LC_X5_Y2_N1; Fanout = 2; COMB Node = 'y_cnt\[1\]~166'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { y_cnt[0]~165 y_cnt[1]~166 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.693 ns y_cnt\[2\]~167 6 COMB LC_X5_Y2_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.693 ns; Loc. = LC_X5_Y2_N2; Fanout = 2; COMB Node = 'y_cnt\[2\]~167'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { y_cnt[1]~166 y_cnt[2]~167 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.816 ns y_cnt\[3\]~168 7 COMB LC_X5_Y2_N3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.123 ns) = 6.816 ns; Loc. = LC_X5_Y2_N3; Fanout = 2; COMB Node = 'y_cnt\[3\]~168'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { y_cnt[2]~167 y_cnt[3]~168 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 7.077 ns y_cnt\[4\]~169 8 COMB LC_X5_Y2_N4 5 " "Info: 8: + IC(0.000 ns) + CELL(0.261 ns) = 7.077 ns; Loc. = LC_X5_Y2_N4; Fanout = 5; COMB Node = 'y_cnt\[4\]~169'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { y_cnt[3]~168 y_cnt[4]~169 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.367 ns) 8.444 ns y_cnt\[9\] 9 REG LC_X5_Y2_N9 5 " "Info: 9: + IC(0.000 ns) + CELL(1.367 ns) = 8.444 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'y_cnt\[9\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.367 ns" { y_cnt[4]~169 y_cnt[9] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.398 ns ( 52.08 % ) " "Info: Total cell delay = 4.398 ns ( 52.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.046 ns ( 47.92 % ) " "Info: Total interconnect delay = 4.046 ns ( 47.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.444 ns" { x_cnt[10] Equal0~66 Equal0~67 y_cnt[0]~165 y_cnt[1]~166 y_cnt[2]~167 y_cnt[3]~168 y_cnt[4]~169 y_cnt[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.444 ns" { x_cnt[10] Equal0~66 Equal0~67 y_cnt[0]~165 y_cnt[1]~166 y_cnt[2]~167 y_cnt[3]~168 y_cnt[4]~169 y_cnt[9] } { 0.000ns 1.328ns 0.716ns 2.002ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.740ns 0.914ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 1.367ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 23 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns y_cnt\[9\] 2 REG LC_X5_Y2_N9 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'y_cnt\[9\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk y_cnt[9] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk y_cnt[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout y_cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 23 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns x_cnt\[10\] 2 REG LC_X5_Y4_N4 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'x_cnt\[10\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk x_cnt[10] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk x_cnt[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout x_cnt[10] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk y_cnt[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout y_cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk x_cnt[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout x_cnt[10] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.444 ns" { x_cnt[10] Equal0~66 Equal0~67 y_cnt[0]~165 y_cnt[1]~166 y_cnt[2]~167 y_cnt[3]~168 y_cnt[4]~169 y_cnt[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.444 ns" { x_cnt[10] Equal0~66 Equal0~67 y_cnt[0]~165 y_cnt[1]~166 y_cnt[2]~167 y_cnt[3]~168 y_cnt[4]~169 y_cnt[9] } { 0.000ns 1.328ns 0.716ns 2.002ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.740ns 0.914ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 1.367ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk y_cnt[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout y_cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk x_cnt[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout x_cnt[10] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk vga_b y_cnt\[0\] 20.879 ns register " "Info: tco from clock \"clk\" to destination pin \"vga_b\" through register \"y_cnt\[0\]\" is 20.879 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 23 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns y_cnt\[0\] 2 REG LC_X5_Y2_N0 9 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N0; Fanout = 9; REG Node = 'y_cnt\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk y_cnt[0] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk y_cnt[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout y_cnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.155 ns + Longest register pin " "Info: + Longest register to pin delay is 17.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y_cnt\[0\] 1 REG LC_X5_Y2_N0 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 9; REG Node = 'y_cnt\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { y_cnt[0] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.978 ns) 2.276 ns Add3~256 2 COMB LC_X6_Y2_N0 2 " "Info: 2: + IC(1.298 ns) + CELL(0.978 ns) = 2.276 ns; Loc. = LC_X6_Y2_N0; Fanout = 2; COMB Node = 'Add3~256'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.276 ns" { y_cnt[0] Add3~256 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.399 ns Add3~258 3 COMB LC_X6_Y2_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.399 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; COMB Node = 'Add3~258'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~256 Add3~258 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.522 ns Add3~246 4 COMB LC_X6_Y2_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.522 ns; Loc. = LC_X6_Y2_N2; Fanout = 2; COMB Node = 'Add3~246'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~258 Add3~246 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 3.337 ns Add3~247 5 COMB LC_X6_Y2_N3 5 " "Info: 5: + IC(0.000 ns) + CELL(0.815 ns) = 3.337 ns; Loc. = LC_X6_Y2_N3; Fanout = 5; COMB Node = 'Add3~247'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add3~246 Add3~247 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.073 ns) + CELL(0.740 ns) 6.150 ns LessThan14~125 6 COMB LC_X5_Y3_N7 1 " "Info: 6: + IC(2.073 ns) + CELL(0.740 ns) = 6.150 ns; Loc. = LC_X5_Y3_N7; Fanout = 1; COMB Node = 'LessThan14~125'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.813 ns" { Add3~247 LessThan14~125 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.740 ns) 7.601 ns LessThan14~126 7 COMB LC_X5_Y3_N4 2 " "Info: 7: + IC(0.711 ns) + CELL(0.740 ns) = 7.601 ns; Loc. = LC_X5_Y3_N4; Fanout = 2; COMB Node = 'LessThan14~126'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.451 ns" { LessThan14~125 LessThan14~126 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.511 ns) 8.869 ns vga_g~595 8 COMB LC_X5_Y3_N1 2 " "Info: 8: + IC(0.757 ns) + CELL(0.511 ns) = 8.869 ns; Loc. = LC_X5_Y3_N1; Fanout = 2; COMB Node = 'vga_g~595'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.268 ns" { LessThan14~126 vga_g~595 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.740 ns) 10.326 ns vga_g~600 9 COMB LC_X5_Y3_N0 1 " "Info: 9: + IC(0.717 ns) + CELL(0.740 ns) = 10.326 ns; Loc. = LC_X5_Y3_N0; Fanout = 1; COMB Node = 'vga_g~600'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { vga_g~595 vga_g~600 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.511 ns) 12.028 ns vga_b~26 10 COMB LC_X4_Y3_N2 2 " "Info: 10: + IC(1.191 ns) + CELL(0.511 ns) = 12.028 ns; Loc. = LC_X4_Y3_N2; Fanout = 2; COMB Node = 'vga_b~26'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.702 ns" { vga_g~600 vga_b~26 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.200 ns) 12.953 ns vga_b~27 11 COMB LC_X4_Y3_N6 1 " "Info: 11: + IC(0.725 ns) + CELL(0.200 ns) = 12.953 ns; Loc. = LC_X4_Y3_N6; Fanout = 1; COMB Node = 'vga_b~27'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.925 ns" { vga_b~26 vga_b~27 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(2.322 ns) 17.155 ns vga_b 12 PIN PIN_34 0 " "Info: 12: + IC(1.880 ns) + CELL(2.322 ns) = 17.155 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'vga_b'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { vga_b~27 vga_b } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/個(gè)人項(xiàng)目/BJ-EPM240學(xué)習(xí)板/實(shí)驗(yàn)板刻盤(pán)資料/實(shí)驗(yàn)例程以及說(shuō)明文檔/7、VGA接口實(shí)驗(yàn)/verilogvga/vga_dis.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.803 ns ( 45.49 % ) " "Info: Total cell delay = 7.803 ns ( 45.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.352 ns ( 54.51 % ) " "Info: Total interconnect delay = 9.352 ns ( 54.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "17.155 ns" { y_cnt[0] Add3~256 Add3~258 Add3~246 Add3~247 LessThan14~125 LessThan14~126 vga_g~595 vga_g~600 vga_b~26 vga_b~27 vga_b } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "17.155 ns" { y_cnt[0] Add3~256 Add3~258 Add3~246 Add3~247 LessThan14~125 LessThan14~126 vga_g~595 vga_g~600 vga_b~26 vga_b~27 vga_b } { 0.000ns 1.298ns 0.000ns 0.000ns 0.000ns 2.073ns 0.711ns 0.757ns 0.717ns 1.191ns 0.725ns 1.880ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.815ns 0.740ns 0.740ns 0.511ns 0.740ns 0.511ns 0.200ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk y_cnt[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout y_cnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "17.155 ns" { y_cnt[0] Add3~256 Add3~258 Add3~246 Add3~247 LessThan14~125 LessThan14~126 vga_g~595 vga_g~600 vga_b~26 vga_b~27 vga_b } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "17.155 ns" { y_cnt[0] Add3~256 Add3~258 Add3~246 Add3~247 LessThan14~125 LessThan14~126 vga_g~595 vga_g~600 vga_b~26 vga_b~27 vga_b } { 0.000ns 1.298ns 0.000ns 0.000ns 0.000ns 2.073ns 0.711ns 0.757ns 0.717ns 1.191ns 0.725ns 1.880ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.815ns 0.740ns 0.740ns 0.511ns 0.740ns 0.511ns 0.200ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}