{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 02 22:37:07 2009 " "Info: Processing started: Fri Jan 02 22:37:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_dis -c vga_dis " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_dis -c vga_dis" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_dis.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_dis.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_dis " "Info: Found entity 1: vga_dis" {  } { { "vga_dis.v" "" { Text "E:/個人項目/BJ-EPM240學(xué)習(xí)板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga_dis " "Info: Elaborating entity \"vga_dis\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 10 vga_dis.v(57) " "Warning (10230): Verilog HDL assignment warning at vga_dis.v(57): truncated value with size 11 to match size of target (10)" {  } { { "vga_dis.v" "" { Text "E:/個人項目/BJ-EPM240學(xué)習(xí)板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "vga_dis.v" "" { Text "E:/個人項目/BJ-EPM240學(xué)習(xí)板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.v" 65 -1 0 } } { "vga_dis.v" "" { Text "E:/個人項目/BJ-EPM240學(xué)習(xí)板/實驗板刻盤資料/實驗例程以及說明文檔/7、VGA接口實驗/verilogvga/vga_dis.v" 70 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "121 " "Info: Implemented 121 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "114 " "Info: Implemented 114 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Allocated 120 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 02 22:37:09 2009 " "Info: Processing ended: Fri Jan 02 22:37:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}