/* ************************************************************************ */
/* Copyright (c) 1997-2001  Evatronix SA                                    */
/* ************************************************************************ */
/* Please review the terms of the license agreement before using this file. */
/* If you are not an authorised user, please destroy this script file and   */
/* notify Evatronix SA immediately that you inadvertently received an       */
/* unauthorised copy.                                                       */
/* ************************************************************************ */

/* ------------------------------------------------------------------------ */
/* Project name         : C8051                                             */
/* Project description  : C8051 Microcontroller Unit                        */
/* File name            : ports.scr                                         */
/* File contents        : Module "PORTS" synthesis                          */
/* Purpose              : Sample Script for Synopsys                        */
/* Design Engineer      : M.B.                                              */
/* Version              : 3.01                                              */
/* Last modification    : 2001-10-01                                        */
/* ------------------------------------------------------------------------ */

module     = "PORTS"
source_dir = "./src/core/"
work_dir   = "./tools/synopsys/work/"
report_dir = "./tools/synopsys/reports/"

sh mkdir work_dir
sh mkdir report_dir
sh mkdir work_dir
define_design_lib C8051_lib -path work_dir

analyze -format vhdl -lib C8051_lib {source_dir + "ports.vhd"}

elaborate PORTS -arch "RTL" -lib C8051_lib -update
current_design = "PORTS.db:PORTS"

create_clock -name "clk" -period 20 -waveform {   "0" "10" } {   "clk" }


set_min_fault_coverage 95  -timing_critical
set_boundary_optimization "PORTS.db:PORTS"
set_flatten false -design {"PORTS.db:PORTS"}
set_structure true -design {"PORTS.db:PORTS"} -boolean true -timing true
set_dont_touch "PORTS.db:PORTS"


write -format db -hierarchy -output work_dir + module + ".db"
compile  -map_effort medium -prioritize_min_paths
current_design = "PORTS.db:PORTS"
write -format db -hierarchy -output work_dir + module + ".db"

write_script > report_dir + module + ".dc"

/* ************************************************************************ */