?? chipram.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : CHIPRAM.VHD
-- File contents : Entity INTERNAL_DATA_MEMORY
-- Architecture SIM of INTERNAL_DATA_MEMORY
-- Purpose : Asynchronous Data Memory
-- Dual Data port
-- Single Address port
--
-- Destination library : C8051_LIB
-- Dependencies : IEEE.STD_LOGIC_1164
--
-- Design Engineer : M.B.
-- Quality Engineer : M.B.
-- Version : 3.01
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity INTERNAL_DATA_MEMORY is
generic (
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 8
);
port (
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
databusi : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
databuso : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end INTERNAL_DATA_MEMORY;
--*******************************************************************--
architecture SIM of INTERNAL_DATA_MEMORY is
subtype MEMORY_ROW is STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
subtype MEMORY_SIZE is NATURAL RANGE 0 TO 2**ADDRWIDTH-1;
type MEMORY_AREA is ARRAY (MEMORY_SIZE) of MEMORY_ROW;
-----------------------------------------------------------------
-- Converts binary vector to INTEGER
-----------------------------------------------------------------
function TO_INTEGER (input : STD_LOGIC_VECTOR) return INTEGER is
variable result : INTEGER;
variable weight : INTEGER;
begin
result:=0;
weight:=1;
for i in input'LOW to input'HIGH loop
if (input(i)='1' or input(i)='H') then
result := result + weight;
end if;
weight := weight * 2;
end loop;
return result;
end TO_INTEGER;
begin
--------------------------------------------------------------------
main :
--------------------------------------------------------------------
process (wr, rd, addrbus, databusi)
variable memory : MEMORY_AREA;
begin
----------------------------------------
-- Memory write
----------------------------------------
if wr='1' then
memory(TO_INTEGER(addrbus)) := TO_X01(databusi);
end if;
----------------------------------------
-- Memory read
----------------------------------------
if rd='1' then
databuso <= memory(TO_INTEGER(addrbus));
else
databuso <= (others => 'Z');
end if;
end process;
end SIM;
--*******************************************************************--
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