?? extstim.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2000 Evatronix Ltd. --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix S.A. immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : EXTSTIM.VHD
-- File contents : Entity EXTERNAL_STIMULATOR
-- Architecture SIM of EXTERNAL_STIMULATOR
-- Purpose : Test vectors stimulator
--
-- Destination library : C8051_LIB
-- Dependencies : IEEE.STD_LOGIC_1164
-- STD.TEXTIO
--
-- Design Engineer : M.B.
-- Quality Engineer : M.B.
-- Version : 3.01
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.ALL;
entity EXTERNAL_STIMULATOR is
generic (
STIMFILE : STRING := "stim.txt"; -- Stimulus file
FILEPATH : STRING := "tests/default"-- Path to the stim file
);
port (
p0 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p1 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p2 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p3 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
rst : out STD_LOGIC;
ea : out STD_LOGIC
);
end EXTERNAL_STIMULATOR;
--*******************************************************************--
architecture SIM of EXTERNAL_STIMULATOR is
--------------------------------------------------------------------
-- Converts CHARACTER to STD_LOGIC_VECTOR
--------------------------------------------------------------------
function TO_STD_LOGIC (char : CHARACTER) return STD_LOGIC is
variable result : STD_LOGIC;
begin
case char is
when 'U'|'u' => result := 'U';
when '0' => result := '0';
when '1' => result := '1';
when 'X'|'x' => result := 'X';
when 'L'|'l' => result := 'L';
when 'H'|'h' => result := 'H';
when 'W'|'w' => result := 'W';
when 'Z'|'z' => result := 'Z';
when '-' => result := '-';
when others => result := 'X';
end case;
return result;
end TO_STD_LOGIC;
--------------------------------------------------------------------
-- Converts STRING to STD_LOGIC_VECTOR
--------------------------------------------------------------------
function TO_STD_LOGIC_VECTOR (input : STRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR(input'range);
begin
for i in input'range loop
result(i):=TO_STD_LOGIC(input(i));
end loop;
return result;
end TO_STD_LOGIC_VECTOR;
--------------------------------------------------------------------
-- Reads vector of STD_LOGIC Characters from text line
--------------------------------------------------------------------
procedure READ (l : inout LINE; value : out STD_LOGIC_VECTOR) is
variable char : CHARACTER;
begin
if l'length>0 then
while l(l'left)=' ' loop
READ(l,char);
end loop;
for i in value'range loop
READ(l,char);
value(i):=TO_STD_LOGIC(char);
end loop;
end if;
end READ;
--------------------------------------------------------------------
-- Reads STD_LOGIC Character from text line
--------------------------------------------------------------------
procedure READ (l : inout LINE; value : out STD_LOGIC) is
variable char : CHARACTER;
begin
if l'length>0 then
while l(l'left)=' ' loop
READ(l,char);
end loop;
READ(l,char);
value:=TO_STD_LOGIC(char);
end if;
end READ;
begin
--------------------------------------------------------------------
main :
--------------------------------------------------------------------
process
file stim : TEXT is in FILEPATH & STIMFILE;
variable l_in : LINE;
variable stop : TIME;
variable vp0 : STD_LOGIC_VECTOR(7 downto 0);
variable vp1 : STD_LOGIC_VECTOR(7 downto 0);
variable vp2 : STD_LOGIC_VECTOR(7 downto 0);
variable vp3 : STD_LOGIC_VECTOR(7 downto 0);
variable vrst : STD_LOGIC;
variable vea : STD_LOGIC;
begin
----------------------------------------
-- Vectors stimulation
----------------------------------------
while not ENDFILE(stim) loop
READLINE(stim, l_in);
if (l_in'length > 0) and (l_in(1)/='-') then
READ(l_in, stop);
READ(l_in, vp0);
READ(l_in, vp1);
READ(l_in, vp2);
READ(l_in, vp3);
READ(l_in, vrst);
READ(l_in, vea);
if NOW < stop then
wait for stop-NOW;
end if;
p0 <= vp0;
p1 <= vp1;
p2 <= vp2;
p3 <= vp3;
rst <= vrst;
ea <= vea;
end if;
end loop;
assert false
report "End of the stimulus file detected."
severity note;
wait;
end process;
end SIM;
--*******************************************************************--
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