?? serial.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : SERIAL.VHD
-- File contents : Entity SERIAL
-- Architecture RTL of SERIAL
-- Purpose : Serial Unit
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.UTILITY
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
--
-- Design Engineer : D.L. A.B. M.B.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00 :
-- 2001-10-01 : added rxd_ff0 input flip-flop
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."+";
use IEEE.STD_LOGIC_UNSIGNED."-";
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity SERIAL is
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
rxdi : in STD_LOGIC; -- Serial receive data
t1ov : in STD_LOGIC; -- Timer 1 overflow output
smod : in STD_LOGIC; -- Baud rate Doubler
riti : out STD_LOGIC; -- Serial rec./trans. flag
-- Serial outputs
rxdo : out STD_LOGIC; -- Serial transmit data
txd : out STD_LOGIC; -- Serial transmit clock
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataser : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end SERIAL;
--*******************************************************************--
architecture RTL of SERIAL is
-----------------------------------------------------------------
-- Serial Port Control register
-----------------------------------------------------------------
signal scon : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Serial Data Buffer
-----------------------------------------------------------------
signal sbuf_t : STD_LOGIC_VECTOR(7 downto 0);
signal sbuf_r : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- rxdi input falling edge detector
-----------------------------------------------------------------
signal rxd_fall : STD_LOGIC;
signal rxd_ff : STD_LOGIC;
signal rxd_ff0 : STD_LOGIC;
signal rxd_val : STD_LOGIC;
signal rxd_vec : STD_LOGIC_VECTOR (2 downto 0);
-----------------------------------------------------------------
-- Clock counter
-----------------------------------------------------------------
signal clk_count : STD_LOGIC_VECTOR (3 downto 0);
signal clk_ov2 : STD_LOGIC;
signal clk_ov12 : STD_LOGIC;
-----------------------------------------------------------------
-- Serial clock
-----------------------------------------------------------------
signal b_clk : STD_LOGIC;
-----------------------------------------------------------------
-- Timer 1 overflow counter
-----------------------------------------------------------------
signal t1ov_rise : STD_LOGIC;
signal t1ov_ff : STD_LOGIC;
-----------------------------------------------------------------
-- Transmit baud counter
-----------------------------------------------------------------
signal t_baud_count : STD_LOGIC_VECTOR (3 downto 0);
signal t_baud_ov : STD_LOGIC;
signal t_baud_clk : STD_LOGIC; -- baud clock for transmit
-----------------------------------------------------------------
-- Transmit shift register
-----------------------------------------------------------------
signal t_shift_reg : STD_LOGIC_VECTOR (10 downto 0);
signal t_shift_clk : STD_LOGIC;
signal t_shift_we : STD_LOGIC;
-----------------------------------------------------------------
-- Transmit shift counter
-----------------------------------------------------------------
signal t_shift_count : STD_LOGIC_VECTOR (3 downto 0);
-----------------------------------------------------------------
-- Transmit control signals
-----------------------------------------------------------------
signal t_start : STD_LOGIC;
signal t_start_m : STD_LOGIC;
-----------------------------------------------------------------
-- Receive baud counter
-----------------------------------------------------------------
signal r_baud_count : STD_LOGIC_VECTOR (3 downto 0);
signal r_baud_ov : STD_LOGIC;
signal r_baud_clk : STD_LOGIC;
-----------------------------------------------------------------
-- Receive shift register
-----------------------------------------------------------------
signal r_shift_reg : STD_LOGIC_VECTOR (10 downto 0);
-----------------------------------------------------------------
-- Receive shift counter
-----------------------------------------------------------------
signal r_shift_count : STD_LOGIC_VECTOR (3 downto 0);
-----------------------------------------------------------------
-- Receive control signal
-----------------------------------------------------------------
signal r_start : STD_LOGIC;
signal r_start_rise : STD_LOGIC;
signal r_start_fall : STD_LOGIC;
signal r_start_ff : STD_LOGIC;
signal ri_fall : STD_LOGIC;
signal ri_ff : STD_LOGIC;
signal receive : STD_LOGIC;
signal r_shift_temp : STD_LOGIC;
signal r_start_ok : STD_LOGIC;
signal baud_r_count : STD_LOGIC;
signal baud_r_clk : STD_LOGIC;
signal baud_r2_clk : STD_LOGIC;
signal xx : STD_LOGIC;
begin
--------------------------------------------------------------------
-- Serial transmit/receive flag
-- interrupt request flag
-- high active output
--------------------------------------------------------------------
riti_drv :
--------------------------------------------------------------------
riti <= scon(0) or scon(1);
--------------------------------------------------------------------
-- Rising edge detection on the t1ov
-- t1ov_rise is high active during single clk period
--------------------------------------------------------------------
t1ov_rise_proc :
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
t1ov_rise <= '0';
t1ov_ff <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Rising edge detection
-------------------------------------
if t1ov = '1' and t1ov_ff = '0' then
t1ov_rise <= '1';
else
t1ov_rise <= '0';
end if;
----------------------------------
-- t1ov_rise flip-flop
----------------------------------
t1ov_ff <= t1ov;
end if;
end if;
end process;
--------------------------------------------------------------------
-- scon register
--------------------------------------------------------------------
scon_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
scon <= SCON_RV;
xx <='1';
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Special function register write
----------------------------------
if (sfrwe='1' and sfraddr=SCON_ID) then
scon <= sfrdatai;
xx <= not (sfrdatai(4) and not (sfrdatai(0)));
else
if scon(7 downto 6)="00" then
if (t_shift_clk='1' and
t_shift_count="0010") then
scon(1) <= '1'; -- transmit interrupt flag
end if;
else
if (t_shift_clk='1' and
t_shift_count="0001") then
scon(1) <= '1'; -- transmit interrupt flag
end if;
end if;
case scon(7 downto 6) is
------------------------------------
-- Mode 0
------------------------------------
when "00" =>
if (
(cycle=2 or
cycle=4 or
cycle=6 or
cycle=8
) and
(phase=4) and
(receive = '1') and
(r_shift_count="0001")
)
then
scon(0) <= '1';
scon(2) <= '1';
xx <='1';
end if;
------------------------------------
-- Modes 1, 2, 3
------------------------------------
when others =>
if (r_start_fall ='1' and r_start_ok ='1') then
scon(2) <= rxd_val;
if scon(5)='1' then
scon(0) <= rxd_val; -- rec. int. flag
else
scon(0) <= '1'; -- rec. int. flag
end if;
end if;
end case;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
sbuf_t_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
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