?? c8051.vhd
字號:
--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : C8051.VHD
-- File contents : Entity C8051
-- Architecture STRUCTURAL of C8051
-- Purpose : Top-level structure of C8051
-- Synthesisable HDL Core
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.UTILITY
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
-- IEEE.STD_LOGIC_ARITH
--
-- Co-design Engineer : M.B. D.K. A.B. D.L.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00 :
-- 2001-10-01 : added OCI ports: debugreq, debugstep, debugprog,
-- : debugack, flush, fetch, acc
-- 2001-10-01 : added OCI unit
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity C8051 is
port (
-- Control signal inputs
clk : in STD_LOGIC; -- Global clock input
reset : in STD_LOGIC; -- Hardware reset input
ea : in STD_LOGIC; -- External Access input
-- Port inputs
p0i : in STD_LOGIC_VECTOR(7 downto 0);
p1i : in STD_LOGIC_VECTOR(7 downto 0);
p2i : in STD_LOGIC_VECTOR(7 downto 0);
p3i : in STD_LOGIC_VECTOR(7 downto 0);
-- Control signal outputs
psen : out STD_LOGIC; -- Ext. Program Store Enable
ale : out STD_LOGIC; -- Ext. Address Latch Enable
-- On-Chip Instrumentation interface
debugreq : in STD_LOGIC; -- debug mode request
debugstep : in STD_LOGIC; -- debug mode single-step
debugprog : in STD_LOGIC; -- debugger program select
debugack : out STD_LOGIC; -- debugger acknowledge signal
flush : out STD_LOGIC; -- branch instruction fetch
fetch : out STD_LOGIC; -- no-branch instruction fetch
acc : out STD_LOGIC_VECTOR(7 downto 0);
-- Port outputs
p0o : out STD_LOGIC_VECTOR(7 downto 0);
p1o : out STD_LOGIC_VECTOR(7 downto 0);
p2o : out STD_LOGIC_VECTOR(7 downto 0);
p3o : out STD_LOGIC_VECTOR(7 downto 0);
-- Internal program memory interface
romdatai : in STD_LOGIC_VECTOR( 7 downto 0);
romaddr : out STD_LOGIC_VECTOR(13 downto 0);
romoe : out STD_LOGIC; -- Memory output enable
-- Internal data memory interface
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
ramdatao : out STD_LOGIC_VECTOR(7 downto 0);
ramaddr : out STD_LOGIC_VECTOR(7 downto 0);
ramwe : out STD_LOGIC; -- Memory write enable
ramoe : out STD_LOGIC; -- Memory output enable
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatao : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : out STD_LOGIC_VECTOR(6 downto 0);
sfrwe : out STD_LOGIC; -- Register write enable
sfroe : out STD_LOGIC -- Register output enable
);
end C8051;
--*******************************************************************--
architecture STRUCTURAL of C8051 is
-----------------------------------------------------------------
-- Aritmetic Logic Unit
-----------------------------------------------------------------
component ALU
port (
-- Global control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- Memory interface
memdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Internal Data Bus
databus : in STD_LOGIC_VECTOR(7 downto 0);
-- ALU output signals
accreg : out STD_LOGIC_VECTOR(7 downto 0);
regsbank : out STD_LOGIC_VECTOR(1 downto 0);
bitvalue : out STD_LOGIC;
cdjump : out STD_LOGIC;
cyflag : out STD_LOGIC;
-- Special function register interface
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrdatao : out STD_LOGIC_VECTOR(7 downto 0);
sfrdataalu : out STD_LOGIC_VECTOR(7 downto 0);
sfrwe : in STD_LOGIC -- SFR write enable
);
end component;
-----------------------------------------------------------------
-- Clock Control Unit
-----------------------------------------------------------------
component CLOCK_CONTROL
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
reset : in STD_LOGIC; -- Hardware reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
parcycle : in STD_LOGIC;
-- Internal reset driver
rsto : out STD_LOGIC;
-- double bit rate enable
smod : out STD_LOGIC;
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataclk : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- Control Processor Unit
-----------------------------------------------------------------
component CONTROL_UNIT
port (
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- ISR input signals
intreq : in STD_LOGIC; -- Interrupt request
-- OCI ports
debugreq : in STD_LOGIC;
debugprog : in STD_LOGIC;
debugprogff : in STD_LOGIC;
debugstep : in STD_LOGIC;
debugstepff : in STD_LOGIC;
debugmode : in STD_LOGIC;
-- Instruction register output
instr : out STD_LOGIC_VECTOR(7 downto 0);
-- Cycle counter output
cycle : out INTEGER range 1 to 8;
nrcycles : out INTEGER range 1 to 8;
phase : out INTEGER range 1 to 6;
parcycle : out STD_LOGIC;
-- program counter increment
pcince : out STD_LOGIC;
-- Instruction decoder output
codefetche : out STD_LOGIC; -- Opcode fetch enable
codefetcheff : out STD_LOGIC; -- Opcode fetch enable flip-flop
datafetche : out STD_LOGIC; -- Data fetch enable
rmwinstr : out STD_LOGIC; -- Read-Modify-Write Instr.
-- ISR control outputs
intack : out STD_LOGIC; -- Interrupt acknowledge flag
intret : out STD_LOGIC; -- Interrupt return flag
intcall : out STD_LOGIC; -- Interrupt call routine
-- Program bus input
memdatai : in STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-----------------------------------------------------------------
-- Interrupt Service Routine Unit
-----------------------------------------------------------------
component ISR
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
phase : in INTEGER range 1 to 6;
instr : in STD_LOGIC_VECTOR(7 downto 0);
-- OCI input signals
debugmode : in STD_LOGIC;
-- Timers/Counters interrupt inputs
tf0 : in STD_LOGIC; -- Timer 0 overflow
tf1 : in STD_LOGIC; -- Timer 1 overflow
-- Serial interface interrupt inputs
riti : in STD_LOGIC; -- Serial Port interrupt
-- External interrupt inputs
ie0 : in STD_LOGIC; -- External 0 interrupt
ie1 : in STD_LOGIC; -- External 1 interrupt
-- Interrupt return signal
intret : in STD_LOGIC;
-- Interrupt acknowledge signal
intack : in STD_LOGIC;
-- Interrupt service location
intvect : out STD_LOGIC_VECTOR(2 downto 0);
-- Interrupt request signal
intreq : out STD_LOGIC;
-- Interrupt acknowledge signals
t0ack : out STD_LOGIC;
t1ack : out STD_LOGIC;
int0ack : out STD_LOGIC;
int1ack : out STD_LOGIC;
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataisr : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- Memory Control Unit
-----------------------------------------------------------------
component MEMORY_CONTROL
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
ea : in STD_LOGIC; -- External Access input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -