/* Synthesis script for M8051 Soft Core (Verilog)         		*//* Copyright Mentor Graphics Corporation and Licensors 1999.	        *//* V3.000/******************************************************************************//* File         :       %M%                                                   *//* Created on   :                                                             *//* Purpose      :       This Synopsys dc_shell script compiles the M8051      *//* Version      :       3.000                                                 *//* Mod Date     :       %G%                                                   *//* Mod History  :       V3.000 - Cell references are from UMC 0.18um library  *//*                             - Simplified compile strategy                  *//*                      V2.200 1 Sep 1999 - Default clock constraints         *//*                                        - Simplified I/O timing constraints *//*                      V2.100 26 Oct 1997 - Use CBA TSMC 0.35 um Library     *//*                                                                            *//******************************************************************************/compile_preserve_sync_resets="true" /* Echo start time */sh date/* Don't use jk flip-flops */   set_dont_use umc18_slow/JKFF*/* Don't use scan flip-flops */   set_dont_use umc18_slow/DFFQS*   set_dont_use umc18_slow/DFFS*/* Don't use flip-flop with tristate output */   set_dont_use umc18_slow/DFF_RB_OE*/* READ VERILOG SOURCE FILES */read -format verilog ../../rtl/m3s001bo.vread -format verilog ../../rtl/m3s002bo.vread -format verilog ../../rtl/m3s005bo.vread -format verilog ../../rtl/m3s006bo.vread -format verilog ../../rtl/m3s007bo.vread -format verilog ../../rtl/m3s009bo.vread -format verilog ../../rtl/m3s013bo.vread -format verilog ../../rtl/m3s014bo.vread -format verilog ../../rtl/m3s018bo.vread -format verilog ../../rtl/m3s019bo.vread -format verilog ../../rtl/m3s022bo.vread -format verilog ../../rtl/m3s023bo.vread -format verilog ../../rtl/m3s024bo.vread -format verilog ../../rtl/m3s025bo.vread -format verilog ../../rtl/m3s027bo.vread -format verilog ../../rtl/m3s029bo.vread -format verilog ../../rtl/m3s030bo.vread -format verilog ../../rtl/m3s031bo.vread -format verilog ../../rtl/m3s032bo.vread -format verilog ../../rtl/m3s033bo.vread -format verilog ../../rtl/m3s034bo.vread -format verilog ../../rtl/m3s035bo.vread -format verilog ../../rtl/m3s039bo.vread -format verilog ../../rtl/m3s040bo.vread -format verilog ../../rtl/m3s041bo.vread -format verilog ../../rtl/m3s003bo.vread -format verilog ../../rtl/m3s004bo.vread -format verilog ../../rtl/m3s008bo.vread -format verilog ../../rtl/m3s011bo.vread -format verilog ../../rtl/m3s016bo.vread -format verilog ../../rtl/m3s020bo.vread -format verilog ../../rtl/m3s028bo.vread -format verilog ../../rtl/m3s010bo.vread -format verilog ../../rtl/m3s015bo.vread -format verilog ../../rtl/m8051.v/* Ungroup Primitive Elements */set_ungroup m3s002bo      /* 1-bit ALU element */set_ungroup m3s041bo      /* 4-bit ALU carry look ahead element */set_ungroup m3s022bo      /* Opcode Decode sub-block */set_ungroup m3s024bo      /* Opcode Decode sub-block */set_ungroup m3s032bo      /* Opcode Decode sub-block */set_ungroup m3s033bo      /* Opcode Decode sub-block */set_ungroup m3s034bo      /* Opcode Decode sub-block */set_ungroup m3s035bo      /* Opcode Decode sub-block */set_ungroup m3s027bo      /* 4-bit sum slice of program counter */set_ungroup m3s040bo      /* 4-bit carry slice of program counter */set_ungroup m3s029bo      /* UART 1-bit counter element */set_ungroup m3s030bo      /* UART Tx Shift register */set_ungroup m3s031bo      /* UART Rx Shift register *//* Uniquify multiple instantiations */current_design "m8051"uniquify/* Apply Constraints for the first pass compilation */current_design "m8051"/* Set interface delays and clock periods */include hier_setup.scr/* Declare multicycle and false paths */include m8051_exp.mcp include m8051_exp.sfp /* Top down hierarchical compilation */current_design m8051compile -map_effort mediumremove_unconnected_ports -blast_buses find( -hierarchy cell, "*")/************************************************************************//*	Write the synthesis results					*//************************************************************************/verilogout_single_bit = userverilogout_equation = falsewrite -hierarchy -f db -output m8051.db/* adapt and write out names */change_names -rules verilog -h > change_name.rpt/* write out verilog */write -h -f verilog -output ../../gates/synop/m8051.v/* write out delay file */write_timing -f sdf-v2.1 -o ../../gates/synop/m8051.sdf /************************************************************************//*      Generate reports                                                *//************************************************************************//* Report Coding Issues */check_design > chk_des.rptreport_design >  m8051warp.rptreport_constraints -verbose > constraint.rptreport_constraints -all_violators > violation_all.rptreport_constraints -all_violators -verbose > violation_verb.rptreport_area >  area.rptcheck_timingreport_timing -path full -delay max -max_paths 5 -nworst 5 > timing.rptsh datequit()