?C0013:
	CLR  	A
	MOV  	dump_auto,A
; 					  dump_memory();break;
			; SOURCE LINE # 61
	LCALL	dump_memory
	LJMP 	?C0001
;             //case 'e': 
;             //case 'E': break;
;             case 'H':
			; SOURCE LINE # 64
; 			case 'h':
			; SOURCE LINE # 65
; 			case '?': help_message();break;
			; SOURCE LINE # 66
?C0016:
	LCALL	help_message
	LJMP 	?C0001
; 			case 'i':
			; SOURCE LINE # 67
; 			case 'I': input_port1();break;
			; SOURCE LINE # 68
?C0018:
	LCALL	input_port1
	LJMP 	?C0001
; 			case ':': loading_ready = 1;
			; SOURCE LINE # 69
?C0019:
	MOV  	loading_ready,#01H
;             case 'L':
			; SOURCE LINE # 70
; 			case 'l': loading_program();break;
			; SOURCE LINE # 71
?C0021:
	LCALL	loading_program
	LJMP 	?C0001
; 			case 'q':
			; SOURCE LINE # 72
; 			case 'Q': quit_program();break;
			; SOURCE LINE # 73
?C0023:
	LCALL	quit_program
	LJMP 	?C0001
; 			case 'r': 
			; SOURCE LINE # 74
; 			case 'R': reset();break;
			; SOURCE LINE # 75
?C0025:
	LCALL	reset
	LJMP 	?C0001
; 			case 't': 
			; SOURCE LINE # 76
;             case 'T': tiny_tcp_main();break;
			; SOURCE LINE # 77
?C0027:
	LCALL	tiny_tcp_main
	LJMP 	?C0001
; 			case 'Z':
			; SOURCE LINE # 78
; 			case 'z': DoS();break;
			; SOURCE LINE # 79
?C0029:
	LCALL	DoS
	LJMP 	?C0001
; 			
; 			case '$': alter_memory();
			; SOURCE LINE # 81
?C0030:
	LCALL	alter_memory
; 					  ei_receive();
			; SOURCE LINE # 82
	LCALL	ei_receive
; 					  ethernet_test();break;
			; SOURCE LINE # 83
	LCALL	ethernet_test
	LJMP 	?C0001
; 			default : break;
			; SOURCE LINE # 84
; 		}
			; SOURCE LINE # 85
; 	}
			; SOURCE LINE # 86
; }
			; SOURCE LINE # 87
	RET  	
; END OF main

CSEG	AT	00003H
	LJMP	RTL8019AS_INT0

; 
; 
; 
; /*****************************************************************************/
; /*		              INTERRUPT SERVICE ROUTINE                              */
; /*****************************************************************************/
; 
; void RTL8019AS_INT0() interrupt 0   /* External Interrupt 0 */

	RSEG  ?PR?RTL8019AS_INT0?MAIN
	USING	0
RTL8019AS_INT0:
	PUSH 	ACC
	PUSH 	B
	PUSH 	DPH
	PUSH 	DPL
	PUSH 	PSW
	PUSH 	AR0
	PUSH 	AR1
	PUSH 	AR2
	PUSH 	AR3
	PUSH 	AR4
	PUSH 	AR5
	PUSH 	AR6
	PUSH 	AR7
			; SOURCE LINE # 95
; {
;     /* you have to use data(Internal RAM) to access faster */
;     /* ENISR_ALL value must be modified when you detect error or success and so on.. */
;     byte e_isr;
;     
;     disable();	/*	EA = 0 global interrupt flag disable   */
			; SOURCE LINE # 101
	CLR  	EA
;     
;     e_isr = EN0_ISR;
			; SOURCE LINE # 103
	MOV  	DPTR,#0307H
	MOVX 	A,@DPTR
	MOV  	R7,A
	MOV  	DPTR,#e_isr?140
	MOVX 	@DPTR,A
;     P1_1 = !P1_1;	/* When it go into interrupt routine, this bit changes 1 and 0 */
			; SOURCE LINE # 104
	CPL  	P1_1
;     time[0].watchdog_counter = 0;	/*  clear to zero to inhibit watchdog */ 
			; SOURCE LINE # 105
	CLR  	A
	MOV  	DPTR,#time
	MOVX 	@DPTR,A
	INC  	DPTR
	MOVX 	@DPTR,A
;     
;     EN_CMD = EN_PAGE0 + EN_NODMA;    
			; SOURCE LINE # 107
	MOV  	DPTR,#0300H
	MOV  	A,#020H
	MOVX 	@DPTR,A
;     
;     if ( e_isr & ( ENISR_OVER ) ) {	/* Receiver overwrote the ring */
			; SOURCE LINE # 109
	MOV  	A,R7
	JNB  	ACC.4,?C0033
; 		ei_rx_overrun();
			; SOURCE LINE # 110
	LCALL	ei_rx_overrun
; 	}
			; SOURCE LINE # 111
	SJMP 	?C0034
?C0033:
; 	else if ( e_isr & (ENISR_RX) ) {		/* Receive without error */
			; SOURCE LINE # 112
	MOV  	DPTR,#e_isr?140
	MOVX 	A,@DPTR
	JNB  	ACC.0,?C0034
; #ifdef RECEIVE_TEST
; 	ei_receive();		
			; SOURCE LINE # 114
	LCALL	ei_receive
; #elif	
; 	receive_test();
; #endif		
; 		EN0_ISR = ENISR_RX;
			; SOURCE LINE # 118
	MOV  	DPTR,#0307H
	MOV  	A,#01H
	MOVX 	@DPTR,A
; 	}	
			; SOURCE LINE # 119
?C0034:
; 	if ( e_isr & ENISR_RX_ERR ) {		
			; SOURCE LINE # 120
	MOV  	DPTR,#e_isr?140
	MOVX 	A,@DPTR
	MOV  	R7,A
	JNB  	ACC.2,?C0036
; 		/* Receiver with error(CRC, frame aligement,FIFO overflow, receive packet failure  */
; 		//print_int("\n\rReceive error..");
; 		EN0_ISR = ENISR_RX_ERR;
			; SOURCE LINE # 123
	MOV  	DPTR,#0307H
	MOV  	A,#04H
	MOVX 	@DPTR,A
; 	}
			; SOURCE LINE # 124
?C0036:
; 	if ( e_isr & ( ENISR_TX ) ) {		/* Transmit without error */
			; SOURCE LINE # 125
	MOV  	A,R7
	JNB  	ACC.1,?C0037
; 		//print_int("\n\rTx OK!");
; 		EN0_ISR = ENISR_TX;
			; SOURCE LINE # 127
	MOV  	DPTR,#0307H
	MOV  	A,#02H
	MOVX 	@DPTR,A
; 	}
			; SOURCE LINE # 128
?C0037:
; 	if ( e_isr & ( ENISR_TX_ERR ) ) {	/* Transmit with error(collision, FIFO underrun) */
			; SOURCE LINE # 129
	MOV  	A,R7
	JNB  	ACC.3,?C0038
; 		//print_int("\n\rTx error..");
; 		EN0_ISR = ENISR_TX_ERR;     /* ? */
			; SOURCE LINE # 131
	MOV  	DPTR,#0307H
	MOV  	A,#08H
	MOVX 	@DPTR,A
; 	}
			; SOURCE LINE # 132
?C0038:
; 	if ( e_isr & ( ENISR_COUNTERS ) ) {
			; SOURCE LINE # 133
	MOV  	A,R7
	JNB  	ACC.5,?C0039
; 		//print_int("\n\rCounter error..");
; 		rx_frame_errors  += EN0_COUNTER0;
			; SOURCE LINE # 135
	MOV  	DPTR,#030DH
	MOVX 	A,@DPTR
	MOV  	R6,A
	MOV  	DPTR,#rx_frame_errors
	MOVX 	A,@DPTR
	ADD  	A,R6
	MOVX 	@DPTR,A
; 		rx_crc_errors    += EN0_COUNTER1;
			; SOURCE LINE # 136
	MOV  	DPTR,#030EH
	MOVX 	A,@DPTR
	MOV  	R6,A
	MOV  	DPTR,#rx_crc_errors
	MOVX 	A,@DPTR
	ADD  	A,R6
	MOVX 	@DPTR,A
; 		rx_missed_errors += EN0_COUNTER2;
			; SOURCE LINE # 137
	MOV  	DPTR,#030FH
	MOVX 	A,@DPTR
	MOV  	R6,A
	MOV  	DPTR,#rx_missed_errors
	MOVX 	A,@DPTR
	ADD  	A,R6
	MOVX 	@DPTR,A
; 		EN0_ISR = ENISR_COUNTERS;	/*  Counters need emptying               */
			; SOURCE LINE # 138
	MOV  	DPTR,#0307H
	MOV  	A,#020H
	MOVX 	@DPTR,A
; 	}
			; SOURCE LINE # 139
?C0039:
; 	if ( e_isr & ( ENISR_RDC ) ) {		/* Remote DMA complete */
			; SOURCE LINE # 140
	MOV  	A,R7
	JNB  	ACC.6,?C0040
; 		EN0_ISR = ENISR_RDC;
			; SOURCE LINE # 141
	MOV  	DPTR,#0307H
	MOV  	A,#040H
	MOVX 	@DPTR,A
; 	}
			; SOURCE LINE # 142
?C0040:
; 	
; 		
; 	EN_CMD = EN_PAGE0 + EN_NODMA + EN_START;
			; SOURCE LINE # 145
	MOV  	DPTR,#0300H
	MOV  	A,#022H
	MOVX 	@DPTR,A
; 	EN0_ISR = 0xff;
			; SOURCE LINE # 146
	MOV  	DPTR,#0307H
	MOV  	A,#0FFH
	MOVX 	@DPTR,A
; 	
; 	//EN0_ISR = ENISR_ALL;
; 	enable();	/*	EA = 1 global interrupt flag enable    */
			; SOURCE LINE # 149
	SETB 	EA
; }
			; SOURCE LINE # 150
	POP  	AR7
	POP  	AR6
	POP  	AR5
	POP  	AR4
	POP  	AR3
	POP  	AR2
	POP  	AR1
	POP  	AR0
	POP  	PSW
	POP  	DPL
	POP  	DPH
	POP  	B
	POP  	ACC
	RETI 	
; END OF RTL8019AS_INT0

CSEG	AT	0000BH
	LJMP	TIMEOUT_T0_INT

; 
; void TIMEOUT_T0_INT() interrupt 1

	RSEG  ?PR?TIMEOUT_T0_INT?MAIN
	USING	0
TIMEOUT_T0_INT:
	PUSH 	ACC
	PUSH 	B
	PUSH 	DPH
	PUSH 	DPL
	PUSH 	PSW
	PUSH 	AR0
	PUSH 	AR1
	PUSH 	AR2
	PUSH 	AR4
	PUSH 	AR5
	PUSH 	AR6
	PUSH 	AR7
			; SOURCE LINE # 152
; {
; 	T0 = !T0;		/* T0 pin	*/
			; SOURCE LINE # 154
	CPL  	T0
; 	clock_MS++;			/* I don't know yet ??*/
			; SOURCE LINE # 155
	MOV  	DPTR,#clock_MS
	MOVX 	A,@DPTR
	MOV  	R4,A
	INC  	DPTR
	MOVX 	A,@DPTR
	MOV  	R5,A
	INC  	DPTR
	MOVX 	A,@DPTR
	MOV  	R6,A
	INC  	DPTR
	MOVX 	A,@DPTR
	MOV  	R2,#00H
	MOV  	R1,#00H
	MOV  	R0,#00H
	ADD  	A,#01H
	MOV  	R7,A
	MOV  	A,R2
	ADDC 	A,R6
	MOV  	R6,A
	MOV  	A,R1
	ADDC 	A,R5
	MOV  	R5,A
	MOV  	A,R0
	ADDC 	A,R4
	MOV  	R4,A
	MOV  	DPTR,#clock_MS
	LCALL	?C?LSTXDATA
; 	TH0 = time[0].reg[0];	/* <-- TIMER0_INTERVAL_HIGH_BYTE  */
			; SOURCE LINE # 156
	MOV  	DPTR,#time
	MOVX 	A,@DPTR
	MOV  	TH0,A
; 	TL0 = time[0].reg[1];	/* <-- TIMER0_INTERVAL_LOW_BYTE   */
			; SOURCE LINE # 157
	INC  	DPTR
	MOVX 	A,@DPTR
	MOV  	TL0,A
; 	if (time[0].watchdog_counter > WATCHDOG){
			; SOURCE LINE # 158
	SETB 	C
	MOVX 	A,@DPTR
	SUBB 	A,#00H
	MOV  	DPTR,#time
	MOVX 	A,@DPTR
	SUBB 	A,#08H
	JC   	?C0042
; 		time[0].watchdog_counter = 0;
			; SOURCE LINE # 159
	CLR  	A
	MOVX 	@DPTR,A
	INC  	DPTR
	MOVX 	@DPTR,A
; 		//print_int("S");
; 		//ethernet_init();
; 		//print_int("\n\rWatchDog bowwow~!!");
; 	}
			; SOURCE LINE # 163
	SJMP 	?C0044
?C0042:
; 	else{
			; SOURCE LINE # 164
; 		time[0].watchdog_counter += 1;
			; SOURCE LINE # 165
	MOV  	DPTR,#time+01H
	MOVX 	A,@DPTR
	INC  	A
	MOVX 	@DPTR,A
	JNZ  	?C0045
	MOV  	DPTR,#time
	MOVX 	A,@DPTR
	INC  	A
	MOVX 	@DPTR,A
?C0045:
; 	}
			; SOURCE LINE # 166
; }
			; SOURCE LINE # 167
?C0044:
	POP  	AR7
	POP  	AR6
	POP  	AR5
	POP  	AR4
	POP  	AR2
	POP  	AR1
	POP  	AR0
	POP  	PSW
	POP  	DPL
	POP  	DPH
	POP  	B
	POP  	ACC
	RETI 	
; END OF TIMEOUT_T0_INT

	END