/*
 * File:		sysinit.c
 * Purpose:		Reset configuration of the M5282EVB
 *
 * Notes:		
 */
//#include "mcf5282.h"
#include "arch.h"
/********************************************************************/
void
mcf5282_init(void)
{
	void mcf5282_wtm_init(void);
	void mcf5282_pll_init(void);
	void mcf5282_scm_init(void);
	void mcf5282_gpio_init(void);
	void mcf5282_uart_init(void);
	void mcf5282_cs_init(void);
	void mcf5282_sdram_init(void);	*((volatile unsigned short *) (0x40100022 )) |= 0x0005;//set PTC2 PTC0 as output	*((volatile unsigned short *) (0x40100024 )) |= 0x0500;//set PTD2 PTD0 as output	mcf5282_wtm_init();	//*((volatile unsigned short *) (0x40100010 )) &= 0xfeff;//D6 light	mcf5282_pll_init();	//*((volatile unsigned short *) (0x40100010 )) &= 0xfbff;//D7 light	mcf5282_scm_init();
	//*((volatile unsigned short *) (0x40100010 )) &= 0xfaff;//D6,D7 light	mcf5282_cs_init();
	//*((volatile unsigned short *) (0x4010000e )) &= 0xfffe;//D8 light	mcf5282_gpio_init();
		mcf5282_uart_init();
	//*((volatile unsigned short *) (0x4010000e )) &= 0xfffa;//D8,D9 light	mcf5282_sdram_init();		//*((volatile unsigned short *) (0x40100010 )) |= 0x0400;	//*((volatile unsigned short *) (0x40100010 )) &= 0xfeff;//D6 light}	/*****************************************	*((volatile unsigned short *) (mbar + )) = 0x0000;	*((volatile unsigned long *) (mbar + )) = 0x003e0000;	*((volatile unsigned char *) (mbar + )) = 0x07;***************************/
void 
mcf5282_wtm_init(void)
{
	/*	 * Disable Software Watchdog Timer	 */	volatile unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;	//MCF5282_WTM_WCR = 0;	*((volatile unsigned short *)(mbar + MCF5282_WTM_WCR)) = 0x0000;}

/********************************************************************/
void 
mcf5282_pll_init(void)
{
	/*
	 * Multiply 8Mhz reference crystal by 8 to acheive system clock of 64Mhz
	 */
	volatile  unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;//	MCF5282_CLOCK_SYNCR = MCF5282_CLOCK_SYNCR_MFD(2);
//	while (!(MCF5282_CLOCK_SYNSR & MCF5282_CLOCK_SYNSR_LOCK));
	*((volatile unsigned short *) (mbar + MCF5282_CLOCK_SYNCR))= MCF5282_CLOCK_SYNCR_MFD(2);while (!(*((volatile unsigned char *) (mbar + MCF5282_CLOCK_SYNSR)) & MCF5282_CLOCK_SYNSR_LOCK));}

/****************************************************************/
void
mcf5282_scm_init(void)
{
	/* 
	 * Enable on-chip modules to access internal SRAM 
	 */
	volatile  unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;	*((volatile unsigned long *) (mbar + MCF5282_SCM_RAMBAR))= MCF5282_SCM_RAMBAR_BDE;
}

/********************************************************************/
void 
mcf5282_gpio_init(void)
{
	/*
	 * When booting from external Flash, the port-size is less than
	 * the port-size of SDRAM.  In this case it is necessary to enable 
	 * Data[23:0] on Ports B, C, and D.
	 */ 
	volatile  unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;		//*((volatile unsigned short *) (0x40100010 )) &= 0xfeff;//D6 light	*((volatile unsigned char *)(mbar + MCF5282_GPIO_PBCDPAR))= (0|MCF5282_GPIO_PBCDPAR_PBPA|MCF5282_GPIO_PBCDPAR_PCDPA);		//*((volatile unsigned short *) (0x40100010 )) &= 0xfbff;//D7 light	/* 
	 * Initialize PEHLPAR to enable Ethernet signals 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_GPIO_PEHLPAR))= 0xC0;		//*((volatile unsigned short *) (0x40100010 )) &= 0xfaff;//D6,D7 light}

/********************************************************************/
void
mcf5282_uart_init(void)
{
	/*
	 * Initialize UART0 for serial communications
	 */
 
	register unsigned short ubgs;	volatile  unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;		/* 
	 * Enable URXD0 and UTXD0 on Port UA
	 */
	*((volatile unsigned char *) (mbar +MCF5282_GPIO_PUAPAR )) = 0x03;

	/* 
	 * Reset Transmitter 
	 */
	*((volatile unsigned char *) (mbar +MCF5282_UART0_UCR)) = MCF5282_UART_UCR_RESET_TX;

	/* 
	 * Reset Receiver 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UCR ))= MCF5282_UART_UCR_RESET_RX;

	/* 
	 * Reset Mode Register 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UCR ))= MCF5282_UART_UCR_RESET_MR;

	/* 
	 * No parity, 8-bits per character 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UMR)) = (0		| MCF5282_UART_UMR1_PM_NONE		| MCF5282_UART_UMR1_BC_8 );
	/* 
	 * No echo or loopback, 1 stop bit 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UMR)) = (0
		| MCF5282_UART_UMR2_CM_NORMAL		| MCF5282_UART_UMR2_STOP_BITS_1);
	/* 
	 * Set Rx and Tx baud by timer 
	 */
	*((volatile unsigned char *) (mbar +MCF5282_UART0_UCSR)) = (0| MCF5282_UART_UCSR_RCS_SYS_CLK		| MCF5282_UART_UCSR_TCS_SYS_CLK);

	/* 
	 * Mask all UART interrupts 
	 */
	*((volatile unsigned char *) (mbar +MCF5282_UART0_UIMR)) = 0;
                 
	/* 
	 * Calculate baud settings 
	 */
	ubgs = (unsigned short)((SYSTEM_CLOCK*1000000)/(19200 * 32));//board_get_baud() * 32
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UBG1 ))= (unsigned char)((ubgs & 0xFF00) >> 8);
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UBG2 ))= (unsigned char)(ubgs & 0x00FF);

	/* 
	 * Enable receiver and transmitter 
	 */
	*((volatile unsigned char *) (mbar + MCF5282_UART0_UCR)) = (0		| MCF5282_UART_UCR_TX_ENABLED		| MCF5282_UART_UCR_RX_ENABLED);}/********************************************************************/
void
mcf5282_sdram_init(void)
{
	int i;
	volatile  unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;
	if (!(*((volatile unsigned long *) (mbar + MCF5282_SDRAMC_DACR0)) & MCF5282_SDRAMC_DACR_RE))
	{
		/* 
		 * Initialize DRAM Control Register: DCR 
		 */
		*((volatile unsigned short *) (mbar + MCF5282_SDRAMC_DCR)) = (0			| MCF5282_SDRAMC_DCR_RTIM_6			| MCF5282_SDRAMC_DCR_RC((15 * SYSTEM_CLOCK)>>4));
		/* 
		 * Initialize DACR0
		 */
		*((volatile unsigned long *) (mbar + MCF5282_SDRAMC_DACR0)) = (0			| MCF5282_SDRAMC_DACR_BASE(0)			| MCF5282_SDRAMC_DACR_CASL(1)			| MCF5282_SDRAMC_DACR_CBM(3)			| MCF5282_SDRAMC_DACR_PS_32);			
		/*
		 * Initialize DMR0
		 */
		*((volatile unsigned long *) (mbar + MCF5282_SDRAMC_DMR0)) = (0			| MCF5282_SDRAMC_DMR_BAM_16M			| MCF5282_SDRAMC_DMR_V);
		/*	
		 * Set IP (bit 3) in DACR 
		 */
		*((volatile unsigned long *)(mbar + MCF5282_SDRAMC_DACR0)) |= MCF5282_SDRAMC_DACR_IP;		/*	
		 * Write to this block to initiate precharge 
		 */
		//*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
		*(unsigned long *)(0) = 0xA5A59696;
		/*	
		 * Set RE (bit 15) in DACR 
		 */
		*((volatile unsigned long *)(mbar + MCF5282_SDRAMC_DACR0)) |= MCF5282_SDRAMC_DACR_RE;			
		/* 
		 * Wait for at least 8 auto refresh cycles to occur 
		 */				for (i = 0; i < 2000; i++)
		{
							asm( "nop");					}

		/*	
		 * Finish the configuration by issuing the IMRS. 
		 */
	*((volatile unsigned long *)(mbar + MCF5282_SDRAMC_DACR0))|= MCF5282_SDRAMC_DACR_IMRS;
		
		/*
		 * Write to the SDRAM Mode Register 
		 */
		*(unsigned long *)(0 + 0x400) = 0xA5A59696;
	}
}
/********************************************************************/
void
mcf5282_cs_init(void)
{
	/* 
	 * ChipSelect 1 - External SRAM 
	 */
	volatile static unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;# if 0*((volatile unsigned short *) (mbar + MCF5282_CS1_CSAR)) = MCF5282_CS_CSAR_BA(EXT_SRAM_ADDRESS);
*((volatile unsigned short *) (mbar + MCF5282_CS1_CSCR))= MCF5282_CS_CSCR_AA | MCF5282_CS_CSCR_PS_32;
*((volatile unsigned long *) (mbar + MCF5282_CS1_CSMR)) = MCF5282_CS_CSMR_BAM_512K | MCF5282_CS_CSMR_V;
#endif	/* 
	 * ChipSelect 0 - External Flash 
	 */ 
*((volatile unsigned short *) (mbar + MCF5282_CS0_CSAR)) = MCF5282_CS_CSAR_BA(0xffe00000);
*((volatile unsigned short *) (mbar + MCF5282_CS0_CSCR))= 0x0da3;	//	(0| MCF5282_CS_CSCR_WS((int)(AMD_FLASH_SPEED/SYSTEM_CLK_PERIOD))
	//	| MCF5282_CS_CSCR_AA
	//	| MCF5282_CS_CSCR_PS_16);
*((volatile unsigned long *) (mbar + MCF5282_CS0_CSMR))= MCF5282_CS_CSMR_BAM_2M | MCF5282_CS_CSMR_V;}void setupBoard(){	volatile unsigned char	*mbar;	mbar = (volatile unsigned char *) MCF_MBAR;	*((volatile unsigned char *)(mbar+MCF5282_EPORT_EPIER))= MCF5282_EPORT_EPIER_EPIE7;	*((volatile unsigned char *)(mbar+MCF5282_INTC0_ICR7)) = MCF5282_INTC_ICR_IL(7);	*((volatile unsigned long *)(mbar+MCF5282_INTC0_IMRL )) &= ~(MCF5282_INTC_INTFRCL_INT7 							| MCF5282_INTC_IMRL_MASKALL);	/* Enable FEC Rx Frame interrupts to ColdFire core */	*((volatile unsigned char *)(mbar+MCF5282_INTC0_ICR27)) = MCF5282_INTC_ICR_IL(4);	*((volatile unsigned char *)(mbar+MCF5282_INTC0_ICR20)) = MCF5282_INTC_ICR_IL(3);		/* Set Timer Interrupt Mask Register */		*((volatile unsigned long *)(mbar+MCF5282_INTC0_IMRL ))&=~(	MCF5282_INTC_IMRL_INT20	| MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);}/********************************************************************/