?? stm32f10x_spi.txt
字號:
000118 8081 STRH r1,[r0,#4]
;;;343 }
;;;344 else
;;;345 {
;;;346 /* Disable the selected SPI SS output */
;;;347 SPIx->CR2 &= CR2_SSOE_Reset;
;;;348 }
;;;349 }
00011a 4770 BX lr
|L1.284|
00011c 8881 LDRH r1,[r0,#4]
00011e f021f021 BIC r1,r1,#4
000122 8081 STRH r1,[r0,#4]
000124 4770 BX lr
;;;350
ENDP
SPI_DataSizeConfig PROC
;;;367 /* Clear DFF bit */
;;;368 SPIx->CR1 &= (u16)~SPI_DataSize_16b;
000126 8802 LDRH r2,[r0,#0]
000128 f422f422 BIC r2,r2,#0x800
00012c 8002 STRH r2,[r0,#0]
;;;369 /* Set new DFF bit value */
;;;370 SPIx->CR1 |= SPI_DataSize;
00012e 8802 LDRH r2,[r0,#0]
000130 4311 ORRS r1,r1,r2
000132 8001 STRH r1,[r0,#0]
;;;371 }
000134 4770 BX lr
;;;372
ENDP
SPI_TransmitCRC PROC
;;;382 /* Enable the selected SPI CRC transmission */
;;;383 SPIx->CR1 |= CR1_CRCNext_Set;
000136 8801 LDRH r1,[r0,#0]
000138 f441f441 ORR r1,r1,#0x1000
00013c 8001 STRH r1,[r0,#0]
;;;384 }
00013e 4770 BX lr
;;;385
ENDP
SPI_CalculateCRC PROC
;;;400
;;;401 if (NewState != DISABLE)
000140 b121 CBZ r1,|L1.332|
;;;402 {
;;;403 /* Enable the selected SPI CRC calculation */
;;;404 SPIx->CR1 |= CR1_CRCEN_Set;
000142 8801 LDRH r1,[r0,#0]
000144 f441f441 ORR r1,r1,#0x2000
000148 8001 STRH r1,[r0,#0]
;;;405 }
;;;406 else
;;;407 {
;;;408 /* Disable the selected SPI CRC calculation */
;;;409 SPIx->CR1 &= CR1_CRCEN_Reset;
;;;410 }
;;;411 }
00014a 4770 BX lr
|L1.332|
00014c 8801 LDRH r1,[r0,#0]
00014e f421f421 BIC r1,r1,#0x2000
000152 8001 STRH r1,[r0,#0]
000154 4770 BX lr
;;;412
ENDP
SPI_GetCRC PROC
;;;431
;;;432 if (SPI_CRC != SPI_CRC_Rx)
000156 2901 CMP r1,#1
000158 d001 BEQ |L1.350|
;;;433 {
;;;434 /* Get the Tx CRC register */
;;;435 crcreg = SPIx->TXCRCR;
00015a 8b00 LDRH r0,[r0,#0x18]
;;;436 }
;;;437 else
;;;438 {
;;;439 /* Get the Rx CRC register */
;;;440 crcreg = SPIx->RXCRCR;
;;;441 }
;;;442
;;;443 /* Return the selected CRC register */
;;;444 return crcreg;
;;;445 }
00015c 4770 BX lr
|L1.350|
00015e 8a80 LDRH r0,[r0,#0x14]
000160 4770 BX lr
;;;446
ENDP
SPI_GetCRCPolynomial PROC
;;;456 /* Return the CRC polynomial register */
;;;457 return SPIx->CRCPR;
000162 8a00 LDRH r0,[r0,#0x10]
;;;458 }
000164 4770 BX lr
;;;459
ENDP
SPI_BiDirectionalLineConfig PROC
;;;477
;;;478 if (SPI_Direction == SPI_Direction_Tx)
000166 f5b1f5b1 CMP r1,#0x4000
00016a d104 BNE |L1.374|
;;;479 {
;;;480 /* Set the Tx only mode */
;;;481 SPIx->CR1 |= SPI_Direction_Tx;
00016c 8801 LDRH r1,[r0,#0]
00016e f441f441 ORR r1,r1,#0x4000
000172 8001 STRH r1,[r0,#0]
;;;482 }
;;;483 else
;;;484 {
;;;485 /* Set the Rx only mode */
;;;486 SPIx->CR1 &= SPI_Direction_Rx;
;;;487 }
;;;488 }
000174 4770 BX lr
|L1.374|
000176 8801 LDRH r1,[r0,#0]
000178 f421f421 BIC r1,r1,#0x4000
00017c 8001 STRH r1,[r0,#0]
00017e 4770 BX lr
;;;489
ENDP
SPI_GetFlagStatus PROC
;;;505 FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG)
;;;506 {
000180 4602 MOV r2,r0
;;;507 FlagStatus bitstatus = RESET;
000182 2000 MOVS r0,#0
;;;508
;;;509 /* Check the parameters */
;;;510 assert(IS_SPI_GET_FLAG(SPI_FLAG));
;;;511
;;;512 /* Check the status of the specified SPI flag */
;;;513 if ((SPIx->SR & SPI_FLAG) != (u16)RESET)
000184 8912 LDRH r2,[r2,#8]
000186 420a TST r2,r1
000188 d000 BEQ |L1.396|
;;;514 {
;;;515 /* SPI_FLAG is set */
;;;516 bitstatus = SET;
00018a 2001 MOVS r0,#1
|L1.396|
;;;517 }
;;;518 else
;;;519 {
;;;520 /* SPI_FLAG is reset */
;;;521 bitstatus = RESET;
;;;522 }
;;;523 /* Return the SPI_FLAG status */
;;;524 return bitstatus;
;;;525 }
00018c 4770 BX lr
;;;526
ENDP
SPI_ClearFlag PROC
;;;544 /* SPI_FLAG_MODF flag clear */
;;;545 if(SPI_FLAG == SPI_FLAG_MODF)
00018e 2920 CMP r1,#0x20
000190 d105 BNE |L1.414|
;;;546 {
;;;547 /* Read SR register */
;;;548 (void)SPIx->SR;
000192 8901 LDRH r1,[r0,#8]
;;;549 /* Write on CR1 register */
;;;550 SPIx->CR1 |= CR1_SPE_Set;
000194 8801 LDRH r1,[r0,#0]
000196 f041f041 ORR r1,r1,#0x40
00019a 8001 STRH r1,[r0,#0]
;;;551 }
;;;552 /* SPI_FLAG_OVR flag clear */
;;;553 else if(SPI_FLAG == SPI_FLAG_OVR)
;;;554 {
;;;555 /* Read SR register */
;;;556 (void)SPIx->SR;
;;;557 }
;;;558 else /* SPI_FLAG_CRCERR flag clear */
;;;559 {
;;;560 /* Clear the selected SPI flag */
;;;561 SPIx->SR &= (u16)~SPI_FLAG;
;;;562 }
;;;563 }
00019c 4770 BX lr
|L1.414|
00019e 2940 CMP r1,#0x40
0001a0 d101 BNE |L1.422|
0001a2 8900 LDRH r0,[r0,#8]
0001a4 4770 BX lr
|L1.422|
0001a6 8902 LDRH r2,[r0,#8]
0001a8 ea22ea22 BIC r1,r2,r1
0001ac 8101 STRH r1,[r0,#8]
0001ae 4770 BX lr
;;;564
ENDP
SPI_GetITStatus PROC
;;;580 {
;;;581 ITStatus bitstatus = RESET;
0001b0 2200 MOVS r2,#0
;;;582 u16 itpos = 0, itmask = 0, enablestatus = 0;
;;;583
;;;584 /* Check the parameters */
;;;585 assert(IS_SPI_GET_IT(SPI_IT));
;;;586
;;;587 /* Get the SPI IT index */
;;;588 itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));
0001b2 f001f001 AND r3,r1,#0xf
0001b6 f04ff04f MOV r12,#1
0001ba fa0cfa0c LSL r3,r12,r3
0001be b29b UXTH r3,r3
;;;589
;;;590 /* Get the SPI IT index */
;;;591 itmask = SPI_IT >> 4;
0001c0 0909 LSRS r1,r1,#4
;;;592 /* Set the IT mask */
;;;593 itmask = (u16)((u16)0x01 << itmask);
0001c2 fa0cfa0c LSL r1,r12,r1
0001c6 b289 UXTH r1,r1
;;;594 /* Get the SPI_IT enable bit status */
;;;595 enablestatus = (SPIx->CR2 & itmask) ;
0001c8 f8b0f8b0 LDRH r12,[r0,#4]
0001cc ea0cea0c AND r1,r12,r1
;;;596
;;;597 /* Check the status of the specified SPI interrupt */
;;;598 if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
0001d0 8900 LDRH r0,[r0,#8]
0001d2 4218 TST r0,r3
0001d4 d001 BEQ |L1.474|
0001d6 b101 CBZ r1,|L1.474|
;;;599 {
;;;600 /* SPI_IT is set */
;;;601 bitstatus = SET;
0001d8 2201 MOVS r2,#1
|L1.474|
;;;602 }
;;;603 else
;;;604 {
;;;605 /* SPI_IT is reset */
;;;606 bitstatus = RESET;
;;;607 }
;;;608 /* Return the SPI_IT status */
;;;609 return bitstatus;
0001da 4610 MOV r0,r2
;;;610 }
0001dc 4770 BX lr
;;;611
ENDP
SPI_ClearITPendingBit PROC
;;;631 /* SPI_IT_MODF pending bit clear */
;;;632 if(SPI_IT == SPI_IT_MODF)
0001de 2955 CMP r1,#0x55
0001e0 d105 BNE |L1.494|
;;;633 {
;;;634 /* Read SR register */
;;;635 (void)SPIx->SR;
0001e2 8901 LDRH r1,[r0,#8]
;;;636 /* Write on CR1 register */
;;;637 SPIx->CR1 |= CR1_SPE_Set;
0001e4 8801 LDRH r1,[r0,#0]
0001e6 f041f041 ORR r1,r1,#0x40
0001ea 8001 STRH r1,[r0,#0]
;;;638 }
;;;639 else if(SPI_IT == SPI_IT_OVR) /* SPI_IT_OVR pending bit clear */
;;;640 {
;;;641 /* Read SR register */
;;;642 (void)(SPIx->SR);
;;;643 }
;;;644 else /* SPI_IT_CRCERR pending bit clear */
;;;645 {
;;;646 /* Get the SPI IT index */
;;;647 itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));
;;;648 /* Clear the selected SPI interrupt pending bits */
;;;649 SPIx->SR &= (u16)~itpos;
;;;650 }
;;;651 }
0001ec 4770 BX lr
|L1.494|
0001ee 2956 CMP r1,#0x56
0001f0 d101 BNE |L1.502|
0001f2 8900 LDRH r0,[r0,#8]
0001f4 4770 BX lr
|L1.502|
0001f6 f001f001 AND r1,r1,#0xf
0001fa 2201 MOVS r2,#1
0001fc fa02fa02 LSL r1,r2,r1
000200 8902 LDRH r2,[r0,#8]
000202 ea22ea22 BIC r1,r2,r1
000206 8101 STRH r1,[r0,#8]
000208 4770 BX lr
;;;652
ENDP
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