;;;160                DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;161      /* Write to DMA Channelx CCR */
;;;162      DMA_Channelx->CCR = tmpreg;
0000da  6002              STR      r2,[r0,#0]
;;;163    
;;;164    /*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
;;;165      /* Write to DMA Channelx CNBTR */
;;;166      DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
0000dc  68ca              LDR      r2,[r1,#0xc]
0000de  6042              STR      r2,[r0,#4]
;;;167    
;;;168    /*--------------------------- DMA Channelx CPAR Configuration ----------------*/
;;;169      /* Write to DMA Channelx CPAR */
;;;170      DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
0000e0  680a              LDR      r2,[r1,#0]
0000e2  6082              STR      r2,[r0,#8]
;;;171    
;;;172    /*--------------------------- DMA Channelx CMAR Configuration ----------------*/
;;;173      /* Write to DMA Channelx CMAR */
;;;174      DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
0000e4  6849              LDR      r1,[r1,#4]
0000e6  60c1              STR      r1,[r0,#0xc]
;;;175    }
0000e8  bc10              POP      {r4}
0000ea  4770              BX       lr
;;;176    
                          ENDP

                  DMA_StructInit PROC
;;;188      /* Initialize the DMA_PeripheralBaseAddr member */
;;;189      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
0000ec  2100              MOVS     r1,#0
0000ee  6001              STR      r1,[r0,#0]
;;;190    
;;;191      /* Initialize the DMA_MemoryBaseAddr member */
;;;192      DMA_InitStruct->DMA_MemoryBaseAddr = 0;
0000f0  6041              STR      r1,[r0,#4]
;;;193    
;;;194      /* Initialize the DMA_DIR member */
;;;195      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
0000f2  6081              STR      r1,[r0,#8]
;;;196    
;;;197      /* Initialize the DMA_BufferSize member */
;;;198      DMA_InitStruct->DMA_BufferSize = 0;
0000f4  60c1              STR      r1,[r0,#0xc]
;;;199    
;;;200      /* Initialize the DMA_PeripheralInc member */
;;;201      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
0000f6  6101              STR      r1,[r0,#0x10]
;;;202    
;;;203      /* Initialize the DMA_MemoryInc member */
;;;204      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
0000f8  6141              STR      r1,[r0,#0x14]
;;;205    
;;;206      /* Initialize the DMA_PeripheralDataSize member */
;;;207      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
0000fa  6181              STR      r1,[r0,#0x18]
;;;208    
;;;209      /* Initialize the DMA_MemoryDataSize member */
;;;210      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
0000fc  61c1              STR      r1,[r0,#0x1c]
;;;211    
;;;212      /* Initialize the DMA_Mode member */
;;;213      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
0000fe  6201              STR      r1,[r0,#0x20]
;;;214    
;;;215      /* Initialize the DMA_Priority member */
;;;216      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000100  6241              STR      r1,[r0,#0x24]
;;;217    
;;;218      /* Initialize the DMA_M2M member */
;;;219      DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
000102  6281              STR      r1,[r0,#0x28]
;;;220    }
000104  4770              BX       lr
;;;221    
                          ENDP

                  DMA_ITConfig PROC
;;;268    
;;;269      if (NewState != DISABLE)
000106  b11a              CBZ      r2,|L1.272|
;;;270      {
;;;271        /* Enable the selected DMA interrupts */
;;;272        DMA_Channelx->CCR |= DMA_IT;
000108  6802              LDR      r2,[r0,#0]
00010a  4311              ORRS     r1,r1,r2
00010c  6001              STR      r1,[r0,#0]
;;;273      }
;;;274      else
;;;275      {
;;;276        /* Disable the selected DMA interrupts */
;;;277        DMA_Channelx->CCR &= ~DMA_IT;
;;;278      }
;;;279    }
00010e  4770              BX       lr
                  |L1.272|
000110  6802              LDR      r2,[r0,#0]
000112  ea22ea22          BIC      r1,r2,r1
000116  6001              STR      r1,[r0,#0]
000118  4770              BX       lr
;;;280    
                          ENDP

                  DMA_GetCurrDataCounter PROC
;;;293      /* Return the current memory address value for Channelx */
;;;294      return ((u16)(DMA_Channelx->CNDTR));
00011a  6840              LDR      r0,[r0,#4]
00011c  b280              UXTH     r0,r0
;;;295    }
00011e  4770              BX       lr
;;;296    
                          ENDP

                  DMA_GetFlagStatus PROC
;;;333    FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
;;;334    {
000120  4601              MOV      r1,r0
;;;335      FlagStatus bitstatus = RESET;
000122  2000              MOVS     r0,#0
;;;336    
;;;337      /* Check the parameters */
;;;338      assert(IS_DMA_GET_FLAG(DMA_FLAG));
;;;339    
;;;340      /* Check the status of the specified DMA flag */
;;;341      if ((DMA->ISR & DMA_FLAG) != (u32)RESET)
000124  4a0a              LDR      r2,|L1.336|
000126  6812              LDR      r2,[r2,#0]
000128  420a              TST      r2,r1
00012a  d000              BEQ      |L1.302|
;;;342      {
;;;343        /* DMA_FLAG is set */
;;;344        bitstatus = SET;
00012c  2001              MOVS     r0,#1
                  |L1.302|
;;;345      }
;;;346      else
;;;347      {
;;;348        /* DMA_FLAG is reset */
;;;349        bitstatus = RESET;
;;;350      }
;;;351      /* Return the DMA_FLAG status */
;;;352      return  bitstatus;
;;;353    }
00012e  4770              BX       lr
;;;354    
                          ENDP

                  DMA_ClearFlag PROC
;;;396      /* Clear the selected DMA flags */
;;;397      DMA->IFCR = DMA_FLAG;
000130  4907              LDR      r1,|L1.336|
000132  6048              STR      r0,[r1,#4]
;;;398    }
000134  4770              BX       lr
;;;399    
                          ENDP

                  DMA_GetITStatus PROC
;;;437    ITStatus DMA_GetITStatus(u32 DMA_IT)
;;;438    {
000136  4601              MOV      r1,r0
;;;439      ITStatus bitstatus = RESET;
000138  2000              MOVS     r0,#0
;;;440    
;;;441      /* Check the parameters */
;;;442      assert(IS_DMA_GET_IT(DMA_IT));
;;;443    
;;;444      /* Check the status of the specified DMA interrupt */
;;;445      if ((DMA->ISR & DMA_IT) != (u32)RESET)
00013a  4a05              LDR      r2,|L1.336|
00013c  6812              LDR      r2,[r2,#0]
00013e  420a              TST      r2,r1
000140  d000              BEQ      |L1.324|
;;;446      {
;;;447        /* DMA_IT is set */
;;;448        bitstatus = SET;
000142  2001              MOVS     r0,#1
                  |L1.324|
;;;449      }
;;;450      else
;;;451      {
;;;452        /* DMA_IT is reset */
;;;453        bitstatus = RESET;
;;;454      }
;;;455      /* Return the DMA_IT status */
;;;456      return  bitstatus;
;;;457    }
000144  4770              BX       lr
;;;458    
                          ENDP

                  DMA_ClearITPendingBit PROC
;;;500      /* Clear the selected DMA interrupt pending bits */
;;;501      DMA->IFCR = DMA_IT;
000146  4902              LDR      r1,|L1.336|
000148  6048              STR      r0,[r1,#4]
;;;502    }
00014a  4770              BX       lr
;;;503    
                          ENDP

                  |L1.332|
00014c  40020044          DCD      0x40020044
                  |L1.336|
000150  40020000          DCD      0x40020000
                  |L1.340|
000154  bffdfff8          DCD      0xbffdfff8