?? stm32f10x_usart.txt
字號:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_usart.o --depend=.\rvmdk\stm32f10x_usart.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_usart.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=1
USART_DeInit PROC
;;;92 void USART_DeInit(USART_TypeDef* USARTx)
;;;93 {
000000 b510 PUSH {r4,lr}
;;;94 switch (*(u32*)&USARTx)
000002 f1a0f1a0 SUB r0,r0,#0x40000000
000006 f5b0f5b0 SUBS r0,r0,#0x4400
00000a d010 BEQ |L1.46|
00000c f5b0f5b0 CMP r0,#0x400
000010 d018 BEQ |L1.68|
000012 f5b0f5b0 CMP r0,#0xf400
000016 d120 BNE |L1.90|
;;;95 {
;;;96 case USART1_BASE:
;;;97 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
000018 2101 MOVS r1,#1
00001a 0388 LSLS r0,r1,#14
00001c f7fff7ff BL RCC_APB2PeriphResetCmd
;;;98 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
000020 e8bde8bd POP {r4,lr}
000024 2100 MOVS r1,#0
000026 f44ff44f MOV r0,#0x4000
00002a f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.46|
;;;99 break;
;;;100
;;;101 case USART2_BASE:
;;;102 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
00002e 2101 MOVS r1,#1
000030 0448 LSLS r0,r1,#17
000032 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;103 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
000036 e8bde8bd POP {r4,lr}
00003a 2100 MOVS r1,#0
00003c f44ff44f MOV r0,#0x20000
000040 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.68|
;;;104 break;
;;;105
;;;106 case USART3_BASE:
;;;107 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
000044 2101 MOVS r1,#1
000046 0488 LSLS r0,r1,#18
000048 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;108 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
00004c e8bde8bd POP {r4,lr}
000050 2100 MOVS r1,#0
000052 f44ff44f MOV r0,#0x40000
000056 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.90|
;;;109 break;
;;;110
;;;111 default:
;;;112 break;
;;;113 }
;;;114 }
00005a bd10 POP {r4,pc}
;;;115
ENDP
USART_Init PROC
;;;127 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
;;;128 {
00005c b530 PUSH {r4,r5,lr}
00005e b085 SUB sp,sp,#0x14
000060 4605 MOV r5,r0
000062 460c MOV r4,r1
;;;129 u32 tmpreg = 0x00, apbclock = 0x00;
;;;130 u32 integerdivider = 0x00;
;;;131 u32 fractionaldivider = 0x00;
;;;132 RCC_ClocksTypeDef RCC_ClocksStatus;
;;;133
;;;134 /* Check the parameters */
;;;135 assert(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
;;;136 assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;137 assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;138 assert(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;139 assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;140 assert(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;141 assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
;;;142 assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
;;;143 assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
;;;144 assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));
;;;145
;;;146 /*---------------------------- USART CR2 Configuration -----------------------*/
;;;147 tmpreg = USARTx->CR2;
000064 8a28 LDRH r0,[r5,#0x10]
;;;148 /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
;;;149 tmpreg &= CR2_CLEAR_Mask;
000066 f24cf24c MOV r1,#0xc0ff
00006a 4008 ANDS r0,r0,r1
;;;150
;;;151 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;152 /* Set STOP[13:12] bits according to USART_Mode value */
;;;153 /* Set CPOL bit according to USART_CPOL value */
;;;154 /* Set CPHA bit according to USART_CPHA value */
;;;155 /* Set LBCL bit according to USART_LastBit value */
;;;156 tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
00006c 88e1 LDRH r1,[r4,#6]
00006e 89e2 LDRH r2,[r4,#0xe]
000070 8a63 LDRH r3,[r4,#0x12]
000072 4311 ORRS r1,r1,r2
000074 8a22 LDRH r2,[r4,#0x10]
000076 431a ORRS r2,r2,r3
000078 4311 ORRS r1,r1,r2
00007a 8aa2 LDRH r2,[r4,#0x14]
00007c 4311 ORRS r1,r1,r2
00007e 4308 ORRS r0,r0,r1
;;;157 USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
;;;158 USART_InitStruct->USART_LastBit;
;;;159
;;;160 /* Write to USART CR2 */
;;;161 USARTx->CR2 = (u16)tmpreg;
000080 8228 STRH r0,[r5,#0x10]
;;;162
;;;163 /*---------------------------- USART CR1 Configuration -----------------------*/
;;;164 tmpreg = 0x00;
;;;165 tmpreg = USARTx->CR1;
000082 89a8 LDRH r0,[r5,#0xc]
;;;166 /* Clear M, PCE, PS, TE and RE bits */
;;;167 tmpreg &= CR1_CLEAR_Mask;
000084 f64ef64e MOV r1,#0xe9f3
000088 4008 ANDS r0,r0,r1
;;;168
;;;169 /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;170 /* Set the M bits according to USART_WordLength value */
;;;171 /* Set PCE and PS bits according to USART_Parity value */
;;;172 /* Set TE and RE bits according to USART_Mode value */
;;;173 tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00008a 88a1 LDRH r1,[r4,#4]
00008c 8922 LDRH r2,[r4,#8]
00008e 4311 ORRS r1,r1,r2
000090 89a2 LDRH r2,[r4,#0xc]
000092 4310 ORRS r0,r0,r2
000094 4308 ORRS r0,r0,r1
;;;174 USART_InitStruct->USART_Mode;
;;;175
;;;176 /* Write to USART CR1 */
;;;177 USARTx->CR1 = (u16)tmpreg;
000096 81a8 STRH r0,[r5,#0xc]
;;;178
;;;179 /*---------------------------- USART CR3 Configuration -----------------------*/
;;;180 tmpreg = 0x00;
;;;181 tmpreg = USARTx->CR3;
000098 8aa8 LDRH r0,[r5,#0x14]
;;;182 /* Clear CTSE and RTSE bits */
;;;183 tmpreg &= CR3_CLEAR_Mask;
00009a f64ff64f MOV r1,#0xfcff
00009e 4008 ANDS r0,r0,r1
;;;184
;;;185 /* Configure the USART HFC -------------------------------------------------*/
;;;186 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;187 tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
0000a0 8961 LDRH r1,[r4,#0xa]
0000a2 4308 ORRS r0,r0,r1
;;;188
;;;189 /* Write to USART CR3 */
;;;190 USARTx->CR3 = (u16)tmpreg;
0000a4 82a8 STRH r0,[r5,#0x14]
;;;191
;;;192 /*---------------------------- USART BRR Configuration -----------------------*/
;;;193 tmpreg = 0x00;
;;;194
;;;195 /* Configure the USART Baud Rate -------------------------------------------*/
;;;196 RCC_GetClocksFreq(&RCC_ClocksStatus);
0000a6 4668 MOV r0,sp
0000a8 f7fff7ff BL RCC_GetClocksFreq
;;;197 if ((*(u32*)&USARTx) == USART1_BASE)
0000ac f1a5f1a5 SUB r0,r5,#0x40000000
0000b0 f5b0f5b0 SUBS r0,r0,#0x13800
0000b4 d101 BNE |L1.186|
;;;198 {
;;;199 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
0000b6 9803 LDR r0,[sp,#0xc]
0000b8 e000 B |L1.188|
|L1.186|
;;;200 }
;;;201 else
;;;202 {
;;;203 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
0000ba 9802 LDR r0,[sp,#8]
|L1.188|
;;;204 }
;;;205
;;;206 /* Determine the integer part */
;;;207 integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
0000bc 2119 MOVS r1,#0x19
0000be 4348 MULS r0,r1,r0
0000c0 6821 LDR r1,[r4,#0]
0000c2 0089 LSLS r1,r1,#2
0000c4 fbb0fbb0 UDIV r1,r0,r1
;;;208 tmpreg = (integerdivider / 0x64) << 0x04;
0000c8 2264 MOVS r2,#0x64
0000ca fbb1fbb1 UDIV r0,r1,r2
0000ce 0100 LSLS r0,r0,#4
;;;209
;;;210 /* Determine the fractional part */
;;;211 fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
0000d0 0903 LSRS r3,r0,#4
0000d2 f06ff06f MVN r12,#0x18
0000d6 fb03fb03 MUL r3,r3,r12
0000da eb01eb01 ADD r1,r1,r3,LSL #2
;;;212 tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
0000de 2332 MOVS r3,#0x32
0000e0 eb03eb03 ADD r1,r3,r1,LSL #4
0000e4 fbb1fbb1 UDIV r1,r1,r2
0000e8 f001f001 AND r1,r1,#0xf
0000ec 4308 ORRS r0,r0,r1
;;;213
;;;214 /* Write to USART BRR */
;;;215 USARTx->BRR = (u16)tmpreg;
0000ee 8128 STRH r0,[r5,#8]
;;;216 }
0000f0 b005 ADD sp,sp,#0x14
0000f2 bd30 POP {r4,r5,pc}
;;;217
ENDP
USART_StructInit PROC
;;;228 /* USART_InitStruct members default value */
;;;229 USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */
0000f4 f44ff44f MOV r1,#0x2580
0000f8 6001 STR r1,[r0,#0]
;;;230 USART_InitStruct->USART_WordLength = USART_WordLength_8b;
0000fa 2100 MOVS r1,#0
0000fc 8081 STRH r1,[r0,#4]
;;;231 USART_InitStruct->USART_StopBits = USART_StopBits_1;
0000fe 80c1 STRH r1,[r0,#6]
;;;232 USART_InitStruct->USART_Parity = USART_Parity_No ;
000100 8101 STRH r1,[r0,#8]
;;;233 USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
000102 8141 STRH r1,[r0,#0xa]
;;;234 USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
000104 220c MOVS r2,#0xc
000106 8182 STRH r2,[r0,#0xc]
;;;235 USART_InitStruct->USART_Clock = USART_Clock_Disable;
000108 81c1 STRH r1,[r0,#0xe]
;;;236 USART_InitStruct->USART_CPOL = USART_CPOL_Low;
00010a 8201 STRH r1,[r0,#0x10]
;;;237 USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;
00010c 8241 STRH r1,[r0,#0x12]
;;;238 USART_InitStruct->USART_LastBit = USART_LastBit_Disable;
00010e 8281 STRH r1,[r0,#0x14]
;;;239 }
000110 4770 BX lr
;;;240
ENDP
USART_Cmd PROC
;;;255
;;;256 if (NewState != DISABLE)
000112 b121 CBZ r1,|L1.286|
;;;257 {
;;;258 /* Enable the selected USART by setting the RUN bit in the CR1 register */
;;;259 USARTx->CR1 |= CR1_RUN_Set;
000114 8981 LDRH r1,[r0,#0xc]
000116 f441f441 ORR r1,r1,#0x2000
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