?? lpc2400.inc
字號(hào):
;/****************************************Copyright (c***************************************************
;** Guangzhou ZHIYUAN electronics Co.,LTD.
;**
;** http://www.embedtools.com
;**
;**--------------File Info--------------------------------------------------------------------------------
;** File name: LPC2400.inc
;** Last modified Date: 2008-04-29
;** Last Version:
;** Descriptions:
;**-------------------------------------------------------------------------------------------------------
;** Created by: LinEnqiang
;** Created date: 2008-04-29
;** Version: 1.0
;** Descriptions: The original version
;**
;**-------------------------------------------------------------------------------------------------------
;** Modified by:
;** Modified date:
;** Version:
;** Descriptions:
;********************************************************************************************************/
;/********************************************************************************************************
; Vectored Interrupt Controller (VIC
;********************************************************************************************************/
VIC_BASE_ADDR EQU 0xFFFFF000
VICIRQStatus EQU (VIC_BASE_ADDR + 0x000)
VICFIQStatus EQU (VIC_BASE_ADDR + 0x004)
VICRawIntr EQU (VIC_BASE_ADDR + 0x008)
VICIntSelect EQU (VIC_BASE_ADDR + 0x00C)
VICIntEnable EQU (VIC_BASE_ADDR + 0x010)
VICIntEnClr EQU (VIC_BASE_ADDR + 0x014)
VICSoftInt EQU (VIC_BASE_ADDR + 0x018)
VICSoftIntClr EQU (VIC_BASE_ADDR + 0x01C)
VICProtection EQU (VIC_BASE_ADDR + 0x020)
VICSWPrioMask EQU (VIC_BASE_ADDR + 0x024)
VICVectAddr0 EQU (VIC_BASE_ADDR + 0x100)
VICVectAddr1 EQU (VIC_BASE_ADDR + 0x104)
VICVectAddr2 EQU (VIC_BASE_ADDR + 0x108)
VICVectAddr3 EQU (VIC_BASE_ADDR + 0x10C)
VICVectAddr4 EQU (VIC_BASE_ADDR + 0x110)
VICVectAddr5 EQU (VIC_BASE_ADDR + 0x114)
VICVectAddr6 EQU (VIC_BASE_ADDR + 0x118)
VICVectAddr7 EQU (VIC_BASE_ADDR + 0x11C)
VICVectAddr8 EQU (VIC_BASE_ADDR + 0x120)
VICVectAddr9 EQU (VIC_BASE_ADDR + 0x124)
VICVectAddr10 EQU (VIC_BASE_ADDR + 0x128)
VICVectAddr11 EQU (VIC_BASE_ADDR + 0x12C)
VICVectAddr12 EQU (VIC_BASE_ADDR + 0x130)
VICVectAddr13 EQU (VIC_BASE_ADDR + 0x134)
VICVectAddr14 EQU (VIC_BASE_ADDR + 0x138)
VICVectAddr15 EQU (VIC_BASE_ADDR + 0x13C)
VICVectAddr16 EQU (VIC_BASE_ADDR + 0x140)
VICVectAddr17 EQU (VIC_BASE_ADDR + 0x144)
VICVectAddr18 EQU (VIC_BASE_ADDR + 0x148)
VICVectAddr19 EQU (VIC_BASE_ADDR + 0x14C)
VICVectAddr20 EQU (VIC_BASE_ADDR + 0x150)
VICVectAddr21 EQU (VIC_BASE_ADDR + 0x154)
VICVectAddr22 EQU (VIC_BASE_ADDR + 0x158)
VICVectAddr23 EQU (VIC_BASE_ADDR + 0x15C)
VICVectAddr24 EQU (VIC_BASE_ADDR + 0x160)
VICVectAddr25 EQU (VIC_BASE_ADDR + 0x164)
VICVectAddr26 EQU (VIC_BASE_ADDR + 0x168)
VICVectAddr27 EQU (VIC_BASE_ADDR + 0x16C)
VICVectAddr28 EQU (VIC_BASE_ADDR + 0x170)
VICVectAddr29 EQU (VIC_BASE_ADDR + 0x174)
VICVectAddr30 EQU (VIC_BASE_ADDR + 0x178)
VICVectAddr31 EQU (VIC_BASE_ADDR + 0x17C)
;/********************************************************************************************************
; The name convention below is from previous LPC2000 family MCUs, in LPC240x,
; these registers are known as "VICVectPriority(x)".)
;********************************************************************************************************/
VICVectPri0 EQU (VIC_BASE_ADDR + 0x200)
VICVectPri1 EQU (VIC_BASE_ADDR + 0x204)
VICVectPri2 EQU (VIC_BASE_ADDR + 0x208)
VICVectPri3 EQU (VIC_BASE_ADDR + 0x20C)
VICVectPri4 EQU (VIC_BASE_ADDR + 0x210)
VICVectPri5 EQU (VIC_BASE_ADDR + 0x214)
VICVectPri6 EQU (VIC_BASE_ADDR + 0x218)
VICVectPri7 EQU (VIC_BASE_ADDR + 0x21C)
VICVectPri8 EQU (VIC_BASE_ADDR + 0x220)
VICVectPri9 EQU (VIC_BASE_ADDR + 0x224)
VICVectPri10 EQU (VIC_BASE_ADDR + 0x228)
VICVectPri11 EQU (VIC_BASE_ADDR + 0x22C)
VICVectPri12 EQU (VIC_BASE_ADDR + 0x230)
VICVectPri13 EQU (VIC_BASE_ADDR + 0x234)
VICVectPri14 EQU (VIC_BASE_ADDR + 0x238)
VICVectPri15 EQU (VIC_BASE_ADDR + 0x23C)
VICVectPri16 EQU (VIC_BASE_ADDR + 0x240)
VICVectPri17 EQU (VIC_BASE_ADDR + 0x244)
VICVectPri18 EQU (VIC_BASE_ADDR + 0x248)
VICVectPri19 EQU (VIC_BASE_ADDR + 0x24C)
VICVectPri20 EQU (VIC_BASE_ADDR + 0x250)
VICVectPri21 EQU (VIC_BASE_ADDR + 0x254)
VICVectPri22 EQU (VIC_BASE_ADDR + 0x258)
VICVectPri23 EQU (VIC_BASE_ADDR + 0x25C)
VICVectPri24 EQU (VIC_BASE_ADDR + 0x260)
VICVectPri25 EQU (VIC_BASE_ADDR + 0x264)
VICVectPri26 EQU (VIC_BASE_ADDR + 0x268)
VICVectPri27 EQU (VIC_BASE_ADDR + 0x26C)
VICVectPri28 EQU (VIC_BASE_ADDR + 0x270)
VICVectPri29 EQU (VIC_BASE_ADDR + 0x274)
VICVectPri30 EQU (VIC_BASE_ADDR + 0x278)
VICVectPri31 EQU (VIC_BASE_ADDR + 0x27C)
VICVectAddr EQU (VIC_BASE_ADDR + 0xF00)
;/********************************************************************************************************
; Pin Connect Block
;********************************************************************************************************/
PINSEL_BASE_ADDR EQU 0xE002C000
PINSEL0 EQU (PINSEL_BASE_ADDR + 0x00)
PINSEL1 EQU (PINSEL_BASE_ADDR + 0x04)
PINSEL2 EQU (PINSEL_BASE_ADDR + 0x08)
PINSEL3 EQU (PINSEL_BASE_ADDR + 0x0C)
PINSEL4 EQU (PINSEL_BASE_ADDR + 0x10)
PINSEL5 EQU (PINSEL_BASE_ADDR + 0x14)
PINSEL6 EQU (PINSEL_BASE_ADDR + 0x18)
PINSEL7 EQU (PINSEL_BASE_ADDR + 0x1C)
PINSEL8 EQU (PINSEL_BASE_ADDR + 0x20)
PINSEL9 EQU (PINSEL_BASE_ADDR + 0x24)
PINSEL10 EQU (PINSEL_BASE_ADDR + 0x28)
PINMODE0 EQU (PINSEL_BASE_ADDR + 0x40)
PINMODE1 EQU (PINSEL_BASE_ADDR + 0x44)
PINMODE2 EQU (PINSEL_BASE_ADDR + 0x48)
PINMODE3 EQU (PINSEL_BASE_ADDR + 0x4C)
PINMODE4 EQU (PINSEL_BASE_ADDR + 0x50)
PINMODE5 EQU (PINSEL_BASE_ADDR + 0x54)
PINMODE6 EQU (PINSEL_BASE_ADDR + 0x58)
PINMODE7 EQU (PINSEL_BASE_ADDR + 0x5C)
PINMODE8 EQU (PINSEL_BASE_ADDR + 0x60)
PINMODE9 EQU (PINSEL_BASE_ADDR + 0x64)
;/********************************************************************************************************
; General Purpose Input/Output (GPIO)
;********************************************************************************************************/
GPIO_BASE_ADDR EQU 0xE0028000
IO0PIN EQU (GPIO_BASE_ADDR + 0x00)
IO0SET EQU (GPIO_BASE_ADDR + 0x04)
IO0DIR EQU (GPIO_BASE_ADDR + 0x08)
IO0CLR EQU (GPIO_BASE_ADDR + 0x0C)
IO1PIN EQU (GPIO_BASE_ADDR + 0x10)
IO1SET EQU (GPIO_BASE_ADDR + 0x14)
IO1DIR EQU (GPIO_BASE_ADDR + 0x18)
IO1CLR EQU (GPIO_BASE_ADDR + 0x1C)
;/********************************************************************************************************
; GPIO Interrupt Registers
;********************************************************************************************************/
IO0IntEnR EQU (GPIO_BASE_ADDR + 0x90)
IO0IntEnF EQU (GPIO_BASE_ADDR + 0x94)
IO0IntStatR EQU (GPIO_BASE_ADDR + 0x84)
IO0IntStatF EQU (GPIO_BASE_ADDR + 0x88)
IO0IntClr EQU (GPIO_BASE_ADDR + 0x8C)
IO2IntEnR EQU (GPIO_BASE_ADDR + 0xB0)
IO2IntEnF EQU (GPIO_BASE_ADDR + 0xB4)
IO2IntStatR EQU (GPIO_BASE_ADDR + 0xA4)
IO2IntStatF EQU (GPIO_BASE_ADDR + 0xA8)
IO2IntClr EQU (GPIO_BASE_ADDR + 0xAC)
IO_INT_STAT EQU (GPIO_BASE_ADDR + 0x80)
IOIntStatus EQU (GPIO_BASE_ADDR + 0x80)
PARTCFG_BASE_ADDR EQU 0x3FFF8000
PARTCFG EQU (PARTCFG_BASE_ADDR + 0x00)
;/********************************************************************************************************
; Fast I/O setup
;********************************************************************************************************/
FIO_BASE_ADDR EQU 0x3FFFC000
FIO0DIR EQU (FIO_BASE_ADDR + 0x00)
FIO0MASK EQU (FIO_BASE_ADDR + 0x10)
FIO0PIN EQU (FIO_BASE_ADDR + 0x14)
FIO0SET EQU (FIO_BASE_ADDR + 0x18)
FIO0CLR EQU (FIO_BASE_ADDR + 0x1C)
FIO1DIR EQU (FIO_BASE_ADDR + 0x20)
FIO1MASK EQU (FIO_BASE_ADDR + 0x30)
FIO1PIN EQU (FIO_BASE_ADDR + 0x34)
FIO1SET EQU (FIO_BASE_ADDR + 0x38)
FIO1CLR EQU (FIO_BASE_ADDR + 0x3C)
FIO2DIR EQU (FIO_BASE_ADDR + 0x40)
FIO2MASK EQU (FIO_BASE_ADDR + 0x50)
FIO2PIN EQU (FIO_BASE_ADDR + 0x54)
FIO2SET EQU (FIO_BASE_ADDR + 0x58)
FIO2CLR EQU (FIO_BASE_ADDR + 0x5C)
FIO3DIR EQU (FIO_BASE_ADDR + 0x60)
FIO3MASK EQU (FIO_BASE_ADDR + 0x70)
FIO3PIN EQU (FIO_BASE_ADDR + 0x74)
FIO3SET EQU (FIO_BASE_ADDR + 0x78)
FIO3CLR EQU (FIO_BASE_ADDR + 0x7C)
FIO4DIR EQU (FIO_BASE_ADDR + 0x80)
FIO4MASK EQU (FIO_BASE_ADDR + 0x90)
FIO4PIN EQU (FIO_BASE_ADDR + 0x94)
FIO4SET EQU (FIO_BASE_ADDR + 0x98)
FIO4CLR EQU (FIO_BASE_ADDR + 0x9C)
;/********************************************************************************************************
; FIOs can be accessed through WORD, HALF-WORD or BYTE.
;********************************************************************************************************/
FIO0DIR0 EQU (FIO_BASE_ADDR + 0x00)
FIO1DIR0 EQU (FIO_BASE_ADDR + 0x20)
FIO2DIR0 EQU (FIO_BASE_ADDR + 0x40)
FIO3DIR0 EQU (FIO_BASE_ADDR + 0x60)
FIO4DIR0 EQU (FIO_BASE_ADDR + 0x80)
FIO0DIR1 EQU (FIO_BASE_ADDR + 0x01)
FIO1DIR1 EQU (FIO_BASE_ADDR + 0x21)
FIO2DIR1 EQU (FIO_BASE_ADDR + 0x41)
FIO3DIR1 EQU (FIO_BASE_ADDR + 0x61)
FIO4DIR1 EQU (FIO_BASE_ADDR + 0x81)
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