`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date:    17:13:36 01/21/2009 // Design Name: // Module Name:    testripple // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////////////////////////////////////////////////////////////////////////////////////module testripple();wire [3:0] Q;
reg clk,reset;

ripple r1(clk, reset , Q[3:0]);

initial begin

reset = 0;
#5;
reset = 1;
#5;
reset = 0;
#5;
clk = 0;
#5;
clk = 1;
#5;clk = 0;#5;clk = 1;
#5;clk = 0;#5;clk = 1;
#5;clk = 0;#5;clk = 1;
#5;clk = 0;#5;clk = 1;
#5;clk = 0;#5;clk = 1;
#5;clk = 0;#5;clk = 1;
endendmodule