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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/USERS/cpld/config.vhd in Library work.Entity <config> (Architecture <config_arch>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <config> (Architecture <config_arch>).Entity <config> analyzed. Unit <config> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <config>.    Related source file is E:/USERS/cpld/config.vhd.WARNING:Xst:1780 - Signal <next_addr> is never used or assigned.WARNING:Xst:1780 - Signal <button_progb> is never used or assigned.    Found 18-bit tristate buffer for signal <fa>.    Found 1-bit tristate buffer for signal <fceb>.    Found 1-bit tristate buffer for signal <foeb>.    Found 1-bit tristate buffer for signal <fweb>.    Found 1-bit tristate buffer for signal <S2_clk>.    Found 1-bit tristate buffer for signal <S2_csb>.    Found 1-bit tristate buffer for signal <S2_wrb>.    Found 18-bit up counter for signal <addr>.    Found 1-bit register for signal <cs>.    Found 8-bit down counter for signal <poweron_cnt>.    Found 1-bit register for signal <poweron_reset>.    Summary:	inferred   2 Counter(s).	inferred   1 D-type flip-flop(s).	inferred  24 Tristate(s).Unit <config> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 2  1-bit register                   : 2# Counters                         : 2  8-bit down counter               : 1  18-bit up counter                : 1# Tristates                        : 7  1-bit tristate buffer            : 6  18-bit tristate buffer           : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <config> ...Completed process "Synthesize".
Started process "Translate".Extracting independent architecture files...Release 6.1i - ngdbuild G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc config.ucf -p xc9500xl config.ngc config.ngdReading NGO file "E:/USERS/cpld/config.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "config.ucf" ...ERROR:NgdBuild:753 - Line 7 in 'config.ucf': Could not find instance(s)   'poweron_cnt_reg<*>' in the design.  To suppress this error specify the   correct instance name or remove the constraint.ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.ERROR:NgdBuild:19 - Errors found while parsing constraint file "config.ucf".Writing NGDBUILD log file "config.bld"...Error: Process "Translate" did not complete.
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Started process "Translate".Release 6.1i - ngdbuild G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc config.ucf -p xc9500xl config.ngc config.ngdReading NGO file "E:/USERS/cpld/config.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "config.ucf" ...ERROR:NgdBuild:753 - Line 7 in 'config.ucf': Could not find instance(s)   'poweron_cnt_reg' in the design.  To suppress this error specify the correct   instance name or remove the constraint.ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.ERROR:NgdBuild:19 - Errors found while parsing constraint file "config.ucf".Writing NGDBUILD log file "config.bld"...Error: Process "Translate" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/USERS/cpld/config.vhd in Library work.Entity <config> (Architecture <config_arch>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <config> (Architecture <config_arch>).Entity <config> analyzed. Unit <config> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <config>.    Related source file is E:/USERS/cpld/config.vhd.WARNING:Xst:1780 - Signal <next_addr> is never used or assigned.WARNING:Xst:1780 - Signal <button_progb> is never used or assigned.    Found 18-bit tristate buffer for signal <fa>.    Found 1-bit tristate buffer for signal <fceb>.    Found 1-bit tristate buffer for signal <foeb>.    Found 1-bit tristate buffer for signal <fweb>.    Found 1-bit tristate buffer for signal <S2_clk>.    Found 1-bit tristate buffer for signal <S2_csb>.    Found 1-bit tristate buffer for signal <S2_wrb>.    Found 18-bit up counter for signal <addr>.    Found 1-bit register for signal <cs>.    Found 8-bit up counter for signal <poweron_cnt>.    Found 1-bit register for signal <poweron_reset>.    Summary:	inferred   2 Counter(s).	inferred   1 D-type flip-flop(s).	inferred  24 Tristate(s).Unit <config> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 2  1-bit register                   : 2# Counters                         : 2  8-bit up counter                 : 1  18-bit up counter                : 1# Tristates                        : 7  1-bit tristate buffer            : 6  18-bit tristate buffer           : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <config> ...Completed process "Synthesize".
Started process "Translate".Release 6.1i - ngdbuild G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc config.ucf -p xc9500xl config.ngc config.ngdReading NGO file "E:/USERS/cpld/config.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "config.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 35728 kilobytesWriting NGD file "config.ngd" ...Writing NGDBUILD log file "config.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.1i - CPLD Optimizer/Partitioner G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Considering device XC9572XL-10-VQ64.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 36 equations into 4 function blocks.......java.lang.RuntimeException: Attempting to format number '0.0' using pattern ''.	at org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063)	at org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071)	at org.apache.xalan.xsltc.runtime.BasisLibrary.formatNumber(BasisLibrary.java:922)	at org.apache.xalan.xsltc.runtime.BasisLibrary.realToString(BasisLibrary.java:870)	at summary.PrintPinResources()	at summary.PrintSummary()	at summary.applyTemplates()	at summary.transform()	at org.apache.xalan.xsltc.runtime.AbstractTranslet.transform(AbstractTranslet.java:540)	at com.xilinx.chipviewer.inout.xslt.XSLTProcess.doTransform(Unknown Source)	at com.xilinx.chipviewer.inout.xslt.XSLTProcess.ProcessXML(Unknown Source)	at com.xilinx.chipviewer.inout.xslt.XSLTProcess.main(Unknown Source)java.lang.ClassCastException: org.apache.xalan.res.XSLTErrorResources_it	at org.apache.xalan.xslt.Process.main(Unknown Source)Exception in thread "main" Design config has been optimized and fit into device XC9572XL-10-VQ64.Completed process "Fit".Started process "Generate Timing".Release 6.1i - Timing Report Generator G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Path tracing .......The number of paths traced: 414...The number of paths traced: 829.Generating TA GUI report ...Generating detailed paths report ...Generating asynchronous checking report ...e:\users\cpld/config_html/tim/timing_report.htm has been created.e:\users\cpld/config_html/tim/timing_report.htm has been created.Release 6.1i - Timing Report Generator G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Path tracing .......The number of paths traced: 414...The number of paths traced: 829.Generating performance summary ...Generating Pad-to-Pad delay section ...Generating Clock-to-Output-Pad delay section ...Generating Setup-To-Clock-At-Pad delay section ...Generating Register-To-Register delay section ...     Cycle time table for clock clk ...config.tim has been created.Generating Stamp model files config.mod, config.data ...config.mod has been created.config.data has been created.Completed process "Generate Timing".
Started process "Generate Programming File".Release 6.1i - Programming File Generator G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Completed process "Generate Programming File".

Project Navigator Auto-Make Log File-------------------------------------

deleting config.lsodeleting config.syrdeleting config.prjdeleting config.sprjdeleting config.anadeleting config.stxdeleting config.cmd_logdeleting config.ngcdeleting config.ngrdeleting __projnav/config_edfTOngd_tcl.rspdeleting config.ngddeleting config.blddeleting config_ngdbuild.navdeleting _ngo/netlist.lstdeleting config.ucf.untfdeleting config_htmldeleting config.cmd_logdeleting __projnav/config_edfTOngd_tcl.rspdeleting config.ngddeleting config.blddeleting config_ngdbuild.navdeleting _ngo/netlist.lstdeleting config.ucf.untfdeleting config_htmldeleting config.cmd_logdeleting config.lsodeleting config.syrdeleting config.prjdeleting config.sprjdeleting config.anadeleting config.stxdeleting config.cmd_logdeleting config.ngcdeleting config.ngrdeleting __projnav/config_edfTOngd_tcl.rspdeleting config.ngddeleting config.blddeleting config_ngdbuild.navdeleting _ngo/netlist.lstdeleting config.ucf.untfdeleting config_htmldeleting config.cmd_logdeleting __projnav/config_vm6TOtim_tcl.rspdeleting config.timdeleting config.moddeleting config.datadeleting config.cmd_logdeleting e:\users\cpld/config_htmldeleting __projnav\taengine.errdeleting __projnav/config_ngdTOvm6_tcl.rspdeleting config.vm6deleting config.cxtdeleting config.blxdeleting config.mfddeleting config.rptdeleting config.logdeleting config.pnxdeleting config.gyddeleting config.xmldeleting config_build.xmldeleting config.ptfdeleting config.bldeleting errors.xmldeleting tmperr.errdeleting config.cmd_logdeleting __projnav/config_vm6TOjed_tcl.rspdeleting config.jeddeleting config.iscdeleting config.cmd_logdeleting config.acedeleting xilinx.sysdeleting config.mpmdeleting config.mcsdeleting config.prmdeleting config.dstdeleting config.exodeleting config.tekdeleting config.hexdeleting config.svfdeleting config.stapldeleting impact.cmddeleting _impact.logdeleting _impact.cmddeleting config.acedeleting xilinx.sysdeleting config.mpmdeleting config.mcsdeleting config.prmdeleting config.dstdeleting config.exodeleting config.tekdeleting config.hexdeleting config.svfdeleting config.stapldeleting impact.cmddeleting _impact.logdeleting _impact.cmddeleting config.prjdeleting config.prjdeleting __projnav/config.xstdeleting ./xstdeleting config.prjdeleting config.prjdeleting __projnav/config.xstdeleting ./xstdeleting __projnav/config.gfldeleting __projnav/config_flowplus.gflFinished cleaning up project