?? ch3example19.mdl
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Model {
Name "ch3example19"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Sat Aug 04 08:44:35 2007"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "shaoyubin"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sat Aug 04 10:01:42 2007"
ModelVersionFormat "1.%<AutoIncrement:6>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "FixedStepDiscrete"
SolverMode "Auto"
StartTime "0.0"
StopTime "100.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "1/1000"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
DataType "auto"
SaturateOnIntegerOverflow on
}
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
SampleTime "-1"
}
Block {
BlockType FrameConversion
OutFrame "Frame-based"
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
ShowAdditionalParam off
AllPortsSameDT on
OutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType RelationalOperator
Operator ">="
ShowAdditionalParam off
InputSameDT on
LogicOutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
ZeroCross on
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType UniformRandomNumber
Minimum "-1"
Maximum "1"
Seed "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType ZeroOrderHold
SampleTime "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "ch3example19"
Location [386, 155, 966, 448]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [15, 33, 95, 77]
FontName "Arial"
FontSize 10
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
P "0.5"
seed "61"
Ts "1/1000"
frameBased off
sampPerFrame "1"
orient off
}
Block {
BlockType Reference
Name "Binary Symmetric\nChannel"
Ports [1, 1]
Position [170, 34, 250, 76]
FontSize 10
SourceBlock "commchan2/Binary Symmetric\nChannel"
SourceType "Binary Symmetric Channel"
P "0.013"
s "71"
E off
}
Block {
BlockType Constant
Name "Constant"
Position [15, 180, 75, 210]
Value "0.013"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [245, 171, 290, 199]
DataType "double"
}
Block {
BlockType Display
Name "Display"
Ports [1]
Position [415, 13, 510, 77]
FontSize 10
Decimation "1"
}
Block {
BlockType Display
Name "Display1"
Ports [1]
Position [415, 143, 510, 207]
FontSize 10
Decimation "1"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2, 1]
Position [310, 21, 385, 74]
FontSize 10
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation1"
Ports [2, 1]
Position [315, 147, 390, 198]
FontSize 10
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [175, 167, 205, 198]
Operator "XOR"
AllPortsSameDT off
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [115, 172, 145, 203]
Operator "<"
InputSameDT off
}
Block {
BlockType UniformRandomNumber
Name "Uniform Random\nNumber"
Position [25, 114, 55, 146]
Minimum "0"
SampleTime "0.001"
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Binary Symmetric\nChannel"
DstPort 1
}
Branch {
Points [0, -45; 155, 0; 0, 25]
DstBlock "Error Rate\nCalculation"
DstPort 1
}
Branch {
Points [0, 65; 35, 0]
Branch {
Points [145, 0]
DstBlock "Error Rate\nCalculation1"
DstPort 1
}
Branch {
Points [0, 55]
DstBlock "Logical\nOperator"
DstPort 1
}
}
}
Line {
SrcBlock "Binary Symmetric\nChannel"
SrcPort 1
Points [40, 0]
DstBlock "Error Rate\nCalculation"
DstPort 2
}
Line {
SrcBlock "Error Rate\nCalculation"
SrcPort 1
Points [0, -5]
DstBlock "Display"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Relational\nOperator"
DstPort 2
}
Line {
SrcBlock "Uniform Random\nNumber"
SrcPort 1
Points [40, 0]
DstBlock "Relational\nOperator"
DstPort 1
}
Line {
SrcBlock "Relational\nOperator"
SrcPort 1
DstBlock "Logical\nOperator"
DstPort 2
}
Line {
SrcBlock "Error Rate\nCalculation1"
SrcPort 1
DstBlock "Display1"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Error Rate\nCalculation1"
DstPort 2
}
Annotation {
Name "BSC二進制對稱信道建模和誤碼率測試模型\n文件名:"
"ch3example19.mdl"
Position [277, 260]
DropShadow on
FontName "Arial"
FontSize 12
}
}
}
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