?? rdio.src
字號:
; .\RDIO.SRC generated from: RDIO.C
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE RDIO.C LARGE WARNINGLEVEL(0) BROWSE INCDIR(D:\UsefulDocument\Mifare\MF RC500\MFRC500 Demo Reader\RC500\For Test) DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOLS SRC(.\RDIO.SRC)
$NOMOD51
NAME RDIO
P0 DATA 080H
P1 DATA 090H
P2 DATA 0A0H
P3 DATA 0B0H
AC BIT 0D0H.6
T0 BIT 0B0H.4
T1 BIT 0B0H.5
EA BIT 0A8H.7
EC BIT 0A8H.6
CH DATA 0F9H
IE DATA 0A8H
CL DATA 0E9H
P0_0 BIT 080H.0
P1_0 BIT 090H.0
P0_1 BIT 080H.1
CCAP0H DATA 0FAH
FL BIT 0D0H.1
P2_0 BIT 0A0H.0
P1_1 BIT 090H.1
P0_2 BIT 080H.2
CCAP1H DATA 0FBH
P3_0 BIT 0B0H.0
P2_1 BIT 0A0H.1
P1_2 BIT 090H.2
P0_3 BIT 080H.3
CCAP2H DATA 0FCH
P3_1 BIT 0B0H.1
P2_2 BIT 0A0H.2
P1_3 BIT 090H.3
P0_4 BIT 080H.4
CCAP3H DATA 0FDH
P3_2 BIT 0B0H.2
P2_3 BIT 0A0H.3
P1_4 BIT 090H.4
P0_5 BIT 080H.5
CCAP4H DATA 0FEH
CCAP0L DATA 0EAH
RD BIT 0B0H.7
P3_3 BIT 0B0H.3
P2_4 BIT 0A0H.4
P1_5 BIT 090H.5
EXF2 BIT 0C8H.6
P0_6 BIT 080H.6
CCAP1L DATA 0EBH
CCAPM0 DATA 0DAH
P3_4 BIT 0B0H.4
P2_5 BIT 0A0H.5
P1_6 BIT 090H.6
P0_7 BIT 080H.7
CCAP2L DATA 0ECH
CCAPM1 DATA 0DBH
P3_5 BIT 0B0H.5
ES BIT 0A8H.4
P2_6 BIT 0A0H.6
P1_7 BIT 090H.7
CCAP3L DATA 0EDH
CCAPM2 DATA 0DCH
P3_6 BIT 0B0H.6
P2_7 BIT 0A0H.7
CCAP4L DATA 0EEH
CCAPM3 DATA 0DDH
IP DATA 0B8H
P3_7 BIT 0B0H.7
CCAPM4 DATA 0DEH
RI BIT 098H.0
CY BIT 0D0H.7
INT0 BIT 0B0H.2
INT1 BIT 0B0H.3
TI BIT 098H.1
RCAP2H DATA 0CBH
PS BIT 0B8H.4
SP DATA 081H
CMOD DATA 0D9H
CCON DATA 0D8H
OV BIT 0D0H.2
RCAP2L DATA 0CAH
WR BIT 0B0H.6
C_T2 BIT 0C8H.1
RCLK BIT 0C8H.5
TCLK BIT 0C8H.4
SBUF DATA 099H
PCON DATA 087H
SCON DATA 098H
TMOD DATA 089H
TCON DATA 088H
IE0 BIT 088H.1
IE1 BIT 088H.3
B DATA 0F0H
AUXR DATA 08EH
CP_RL2 BIT 0C8H.0
ACC DATA 0E0H
ET0 BIT 0A8H.1
ET1 BIT 0A8H.3
TF0 BIT 088H.5
ET2 BIT 0A8H.5
TF1 BIT 088H.7
RB8 BIT 098H.2
TF2 BIT 0C8H.7
TH0 DATA 08CH
EX0 BIT 0A8H.0
IT0 BIT 088H.0
TH1 DATA 08DH
EX1 BIT 0A8H.2
TB8 BIT 098H.3
IT1 BIT 088H.2
TH2 DATA 0CDH
P BIT 0D0H.0
SM0 BIT 098H.7
TL0 DATA 08AH
SM1 BIT 098H.6
TL1 DATA 08BH
SM2 BIT 098H.5
TL2 DATA 0CCH
PT0 BIT 0B8H.1
RS0 BIT 0D0H.3
PT1 BIT 0B8H.3
RS1 BIT 0D0H.4
PT2 BIT 0B8H.5
TR0 BIT 088H.4
TR1 BIT 088H.6
PX0 BIT 0B8H.0
TR2 BIT 0C8H.2
PX1 BIT 0B8H.2
DPH DATA 083H
DPL DATA 082H
IPH DATA 0B7H
EXEN2 BIT 0C8H.3
REN BIT 098H.4
T2MOD DATA 0C9H
T2CON DATA 0C8H
SADEN DATA 0B9H
RXD BIT 0B0H.0
PMR DATA 0C4H
SADDR DATA 0A9H
TXD BIT 0B0H.1
AUXR1 DATA 0A2H
F0 BIT 0D0H.5
PSW DATA 0D0H
?PR?OpenIO?RDIO SEGMENT CODE
?PR?CloseIO?RDIO SEGMENT CODE
?PR?_WriteIO?RDIO SEGMENT CODE
?PR?_ReadIO?RDIO SEGMENT CODE
?XD?RDIO SEGMENT XDATA
?PR?_WriteIOBlock?RDIO SEGMENT CODE
?XD?_WriteIOBlock?RDIO SEGMENT XDATA OVERLAYABLE
?PR?_ReadIOBlock?RDIO SEGMENT CODE
?XD?_ReadIOBlock?RDIO SEGMENT XDATA OVERLAYABLE
?C_INITSEG SEGMENT CODE
EXTRN CODE (?C?CLDOPTR)
EXTRN CODE (?C?CSTOPTR)
PUBLIC ini
PUBLIC GpBase
PUBLIC _ReadIOBlock
PUBLIC _WriteIOBlock
PUBLIC _ReadIO
PUBLIC _WriteIO
PUBLIC CloseIO
PUBLIC OpenIO
XSEG AT 07F00H
ini: DS 1
RSEG ?XD?_ReadIOBlock?RDIO
?_ReadIOBlock?BYTE:
len?548: DS 2
RSEG ?XD?RDIO
cnt?549: DS 2
RSEG ?XD?_WriteIOBlock?RDIO
?_WriteIOBlock?BYTE:
Addr_Data?444: DS 3
len?445: DS 2
RSEG ?XD?RDIO
cnt?446: DS 2
RSEG ?XD?RDIO
c?343: DS 1
GpBase: DS 2
RSEG ?C_INITSEG
DB 042H
DW GpBase
DW ini + 0
; ///////////////////////////////////////////////////////////////////////////////
; // Copyright (c), Philips Semiconductors Gratkorn
; //
; // (C)PHILIPS Electronics N.V.2000
; // All rights are reserved. Reproduction in whole or in part is
; // prohibited without the written consent of the copyright owner.
; // Philips reserves the right to make changes without notice at any time.
; // Philips makes no warranty, expressed, implied or statutory, including but
; // not limited to any implied warranty of merchantibility or fitness for any
; //particular purpose, or that the use will not infringe any third party patent,
; // copyright or trademark. Philips must not be liable for any loss or damage
; // arising from its use.
; ///////////////////////////////////////////////////////////////////////////////
; #include <rdio.h>
; //#include <main.h>
; #include <p89c51rx.h>
;
; ///////////////////////////////////////////////////////////////////////////////
; // Module Definitions
; ///////////////////////////////////////////////////////////////////////////////
; #define GetRegPage(adr) (0x80 | (adr>>3))
;
; unsigned char xdata ini _at_ 0x7f00; // move base address to 0x7f00
; unsigned char xdata *GpBase = &ini ; // redirect pointer to base address
;
; ///////////////////////////////////////////////////////////////////////////////
; // Open Reader Communication
; ///////////////////////////////////////////////////////////////////////////////
; char OpenIO(void)
RSEG ?PR?OpenIO?RDIO
OpenIO:
USING 0
; SOURCE LINE # 29
; {
; SOURCE LINE # 30
; GpBase = &ini;
; SOURCE LINE # 31
MOV DPTR,#GpBase
MOV A,#HIGH (ini)
MOVX @DPTR,A
INC DPTR
MOV A,#LOW (ini)
MOVX @DPTR,A
; P2_7 = 0; // Enable the CS for RC500
; SOURCE LINE # 32
SETB P2_7
; return 0x00;
; SOURCE LINE # 33
MOV R7,#00H
; }
; SOURCE LINE # 34
?C0001:
RET
; END OF OpenIO
;
; ///////////////////////////////////////////////////////////////////////////////
; // Close Reader Communication
; ///////////////////////////////////////////////////////////////////////////////
; void CloseIO(void)
RSEG ?PR?CloseIO?RDIO
CloseIO:
; SOURCE LINE # 39
; {
; SOURCE LINE # 40
; GpBase = 0xff00;
; SOURCE LINE # 41
MOV DPTR,#GpBase
MOV A,#0FFH
ORL AUXR,#02H
MOVX @DPTR,A
ANL AUXR,#0FDH
INC DPTR
CLR A
MOVX @DPTR,A
; P2_7 = 1; // disable the CS for RC500
; SOURCE LINE # 42
SETB P2_7
; }
; SOURCE LINE # 43
RET
; END OF CloseIO
;
; ///////////////////////////////////////////////////////////////////////////////
; // G E N E R I C W R I T E
; ///////////////////////////////////////////////////////////////////////////////
; void WriteIO(unsigned char Address, unsigned char data value)
RSEG ?PR?_WriteIO?RDIO
_WriteIO:
USING 0
; SOURCE LINE # 48
;---- Variable 'value?241' assigned to Register 'R5' ----
;---- Variable 'Address?240' assigned to Register 'R7' ----
; {
; SOURCE LINE # 49
; AUXR |=0x02;
; SOURCE LINE # 50
; WriteRawIO(Address,value);
; SOURCE LINE # 51
MOV DPTR,#GpBase
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
ADD A,R7
MOV DPL,A
CLR A
ADDC A,R4
MOV DPH,A
MOV A,R5
ORL AUXR,#02H
MOVX @DPTR,A
; AUXR &=0xfd; // write value at the specified
; SOURCE LINE # 52
ANL AUXR,#0FDH
; // address
; }
; SOURCE LINE # 54
RET
; END OF _WriteIO
;
; ///////////////////////////////////////////////////////////////////////////////
; // G E N E R I C R E A D
; ///////////////////////////////////////////////////////////////////////////////
; unsigned char ReadIO(unsigned char data Address)
RSEG ?PR?_ReadIO?RDIO
_ReadIO:
USING 0
; SOURCE LINE # 59
;---- Variable 'Address?342' assigned to Register 'R7' ----
; {
; SOURCE LINE # 60
; static unsigned char c;
; AUXR |=0x02;
; SOURCE LINE # 62
; c = ReadRawIO(Address); // read value at the specified
; SOURCE LINE # 63
MOV DPTR,#GpBase
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
ADD A,R7
MOV DPL,A
CLR A
ADDC A,R4
MOV DPH,A
ORL AUXR,#02H
MOVX A,@DPTR
ANL AUXR,#0FDH
MOV DPTR,#c?343
MOVX @DPTR,A
; AUXR &=0xfd; // address
; SOURCE LINE # 64
; return c;
; SOURCE LINE # 65
MOVX A,@DPTR
MOV R7,A
; }
; SOURCE LINE # 66
?C0004:
RET
; END OF _ReadIO
;
; #ifndef SEC_NO_MICORE
; ///////////////////////////////////////////////////////////////////////////////
; // W R I T E S E V E R A L M E M O R Y L O C A T I O N S
; ///////////////////////////////////////////////////////////////////////////////
; void WriteIOBlock(unsigned char *Addr_Data, unsigned short len)
RSEG ?PR?_WriteIOBlock?RDIO
_WriteIOBlock:
USING 0
; SOURCE LINE # 72
MOV DPTR,#Addr_Data?444
MOV A,R3
MOVX @DPTR,A
INC DPTR
MOV A,R2
MOVX @DPTR,A
INC DPTR
MOV A,R1
MOVX @DPTR,A
INC DPTR
MOV A,R4
MOVX @DPTR,A
INC DPTR
MOV A,R5
MOVX @DPTR,A
; {
; SOURCE LINE # 73
; static unsigned short cnt;
;
; for (cnt = 0; cnt < len; cnt++)
; SOURCE LINE # 76
CLR A
MOV DPTR,#cnt?446
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
?C0005:
MOV DPTR,#len?445
MOVX A,@DPTR
MOV R6,A
INC DPTR
MOVX A,@DPTR
MOV R7,A
MOV DPTR,#cnt?446
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
MOV R5,A
CLR C
SUBB A,R7
MOV A,R4
SUBB A,R6
JNC ?C0008
; {
; SOURCE LINE # 77
; // write value at the specified address
; WriteRawIO(Addr_Data[cnt*2],Addr_Data[cnt * 2 + 1]);
; SOURCE LINE # 79
MOV A,R5
ADD A,ACC
MOV R7,A
MOV A,R4
RLC A
MOV R6,A
MOV A,R7
ADD A,#01H
MOV R7,A
CLR A
ADDC A,R6
MOV R6,A
MOV DPTR,#Addr_Data?444
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPL,R7
MOV DPH,R6
LCALL ?C?CLDOPTR
MOV R5,A
MOV DPTR,#cnt?446+01H
MOVX A,@DPTR
ADD A,ACC
MOV R7,A
MOV DPTR,#cnt?446
MOVX A,@DPTR
RLC A
MOV DPL,R7
MOV DPH,A
LCALL ?C?CLDOPTR
MOV R7,A
MOV DPTR,#GpBase
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
ADD A,R7
MOV DPL,A
CLR A
ADDC A,R2
MOV DPH,A
MOV A,R5
ORL AUXR,#02H
MOVX @DPTR,A
ANL AUXR,#0FDH
; }
; SOURCE LINE # 80
MOV DPTR,#cnt?446+01H
MOVX A,@DPTR
INC A
MOVX @DPTR,A
JNZ ?C0005
MOV DPTR,#cnt?446
MOVX A,@DPTR
INC A
MOVX @DPTR,A
?C0013:
SJMP ?C0005
; }
; SOURCE LINE # 81
?C0008:
RET
; END OF _WriteIOBlock
;
; ///////////////////////////////////////////////////////////////////////////////
; // R E A D S E V E R A L M E M O R Y L O C A T I O N S
; ///////////////////////////////////////////////////////////////////////////////
; void ReadIOBlock(unsigned char* Addr_Data, unsigned short len)
RSEG ?PR?_ReadIOBlock?RDIO
_ReadIOBlock:
USING 0
; SOURCE LINE # 86
MOV DPTR,#len?548
MOV A,R4
MOVX @DPTR,A
INC DPTR
MOV A,R5
MOVX @DPTR,A
;---- Variable 'Addr_Data?547' assigned to Register 'R1/R2/R3' ----
; {
; SOURCE LINE # 87
; static unsigned short cnt;
;
; for (cnt = 0; cnt < len; cnt)
; SOURCE LINE # 90
CLR A
MOV DPTR,#cnt?549
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
?C0009:
MOV DPTR,#len?548
MOVX A,@DPTR
MOV R6,A
INC DPTR
MOVX A,@DPTR
MOV R7,A
MOV DPTR,#cnt?549
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
MOV R5,A
CLR C
SUBB A,R7
MOV A,R4
SUBB A,R6
JNC ?C0012
; {
; SOURCE LINE # 91
; Addr_Data[cnt*2 + 1] = ReadRawIO(Addr_Data[cnt*2]);// read value at the
; SOURCE LINE # 92
MOV A,R5
ADD A,ACC
MOV R7,A
MOV A,R4
RLC A
MOV DPL,R7
MOV DPH,A
LCALL ?C?CLDOPTR
MOV R7,A
MOV DPTR,#GpBase
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
ADD A,R7
MOV DPL,A
CLR A
ADDC A,R4
MOV DPH,A
ORL AUXR,#02H
MOVX A,@DPTR
ANL AUXR,#0FDH
MOV R5,A
MOV DPTR,#cnt?549+01H
MOVX A,@DPTR
ADD A,ACC
MOV R7,A
MOV DPTR,#cnt?549
MOVX A,@DPTR
RLC A
MOV DPL,R7
MOV DPH,A
INC DPTR
MOV A,R5
LCALL ?C?CSTOPTR
; // specified address
; }
; SOURCE LINE # 94
SJMP ?C0009
; }
; SOURCE LINE # 95
?C0012:
RET
; END OF _ReadIOBlock
END
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