/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.2.2 EDK_Gm.13.6
* DO NOT EDIT.
*
* Copyright (c) 2003 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/

#define STDIN_BASEADDRESS 0xFFFF0000
#define STDOUT_BASEADDRESS 0xFFFF0000

/******************************************************************/

#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_MYUART_BASEADDR 0xFFFF0000
#define XPAR_MYUART_HIGHADDR 0xFFFF00FF
#define XPAR_MYUART_DEVICE_ID 0
#define XPAR_MYUART_BAUDRATE 19200
#define XPAR_MYUART_USE_PARITY 0
#define XPAR_MYUART_ODD_PARITY 1
#define XPAR_MYUART_DATA_BITS 8

/******************************************************************/

#define XPAR_XGPIO_NUM_INSTANCES 3
#define XPAR_MYGPIO_A_BASEADDR 0xFFFF0400
#define XPAR_MYGPIO_A_HIGHADDR 0xFFFF05FF
#define XPAR_MYGPIO_A_DEVICE_ID 0
#define XPAR_MYGPIO_B_BASEADDR 0xFFFF0600
#define XPAR_MYGPIO_B_HIGHADDR 0xFFFF07FF
#define XPAR_MYGPIO_B_DEVICE_ID 1
#define XPAR_MYGPIO_C_BASEADDR 0xFFFF0800
#define XPAR_MYGPIO_C_HIGHADDR 0xFFFF09FF
#define XPAR_MYGPIO_C_DEVICE_ID 2

/******************************************************************/

#define XPAR_DEBUG_MODULE_BASEADDR 0xFFFF0200
#define XPAR_DEBUG_MODULE_HIGHADDR 0xFFFF02FF

/******************************************************************/

#define XPAR_XTMRCTR_NUM_INSTANCES 2
#define XPAR_MYTIMER1_BASEADDR 0xFFFF0300
#define XPAR_MYTIMER1_HIGHADDR 0xFFFF03FF
#define XPAR_MYTIMER1_DEVICE_ID 0
#define XPAR_MYTIMER2_BASEADDR 0xFFFF0100
#define XPAR_MYTIMER2_HIGHADDR 0xFFFF01FF
#define XPAR_MYTIMER2_DEVICE_ID 1

/******************************************************************/

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
#define XPAR_INTC_SINGLE_BASEADDR 0xFFFF0A00
#define XPAR_INTC_SINGLE_HIGHADDR 0xFFFF0AFF
#define XPAR_XINTC_USE_DCR 0
#define XPAR_XINTC_NUM_INSTANCES 1
#define XPAR_MYINTC_BASEADDR 0xFFFF0A00
#define XPAR_MYINTC_HIGHADDR 0xFFFF0AFF
#define XPAR_MYINTC_KIND_OF_INTR 0x00000000

/******************************************************************/

#define XPAR_MYTIMER2_INTERRUPT_MASK 0X000001
#define XPAR_MYTIMER1_INTERRUPT_MASK 0X000002

/******************************************************************/