library ieee;
use ieee.std_logic_1164.all;

entity dcm_ip is
  port 	(
		clk_in 	: in std_logic;
		clk0_out 	: out std_logic;
		clkdv_out 	: out std_logic;
		clkfx_out 	: out std_logic
		);
end entity dcm_ip;

architecture dcm_ip_arch of dcm_ip is



component DCM
-- synthesis translate_off

generic (CLK_FEEDBACK :string := "1X";
		CLKDV_DIVIDE : real := 2.0;
		CLKFX_DIVIDE : integer :=1;
		CLKFX_MULTIPLY : integer := 1;
		CLKIN_DIVIDE_BY_2 : boolean := FALSE;
		CLKOUT_PHASE_SHIFT: string := "NONE";
		DESKEW_ADJUST: string := "SYSTEM_SYNCHRONOUS";
		DFS_FREQUENCY_MODE: string := "LOW";
		DLL_FREQUENCY_MODE: string := "LOW";
		DSS_MODE: string := "NONE";
		DUTY_CYCLE_CORRECTION : Boolean := TRUE;
		FACTORY_JF : bit_vector := X"C080";
		PHASE_SHIFT: real := 0;
		STARTUP_WAIT :boolean := FALSE);

-- synthesis translate_on

   port ( CLKIN     : in std_logic;
         CLKFB      : in std_logic;
         DSSEN      : in std_logic;
         PSINCDEC   : in std_logic;
         PSEN       : in std_logic;
         PSCLK      : in std_logic;
         RST        : in std_logic;
         CLK0       : out std_logic;
         CLK90      : out std_logic;
         CLK180     : out std_logic;
         CLK270     : out std_logic;
         CLK2X      : out std_logic;
         CLK2X180   : out std_logic;
         CLKDV      : out std_logic;
         CLKFX      : out std_logic;
         CLKFX180   : out std_logic;
         LOCKED     : out std_logic;
         PSDONE     : out std_logic;
         STATUS     : out std_logic_vector(7 downto 0)
  );
end component DCM;
  


  component BUFG
      port (
	  O : out std_logic;
	  I : in std_logic
      );
  end component;

  
  signal clk0_i, clkdv_i, clkfx_i : std_logic;
  signal clk0_int, clkdv_int, clkfx_int : std_logic;


begin


    
    DCM_I: DCM
		port map(
	 			CLKIN  		=> clk_in,
         		CLKFB  		=> clk0_i,
         		DSSEN  		=> '0',
         		PSINCDEC   	=> '0',
         		PSEN       	=> '0',
         		PSCLK      	=> '0',
         		RST        	=> '0',
         		CLK0       	=> clk0_int,
         		CLK90      	=> open,
         		CLK180     	=> open,
         		CLK270     	=> open,
         		CLK2X      	=> open,
         		CLK2X180   	=> open,
         		CLKDV      	=> clkdv_int,
         		CLKFX      	=> clkfx_int,
         		CLKFX180   	=> open,
         		LOCKED     	=> open,
         		PSDONE     	=> open,
         		STATUS     	=> open
  				);
    
  BUFG_CLK0 : BUFG
      port map (
	  			O => clk0_i,
	  			I => clk0_int
				);
  
  BUFG_CLKDV : BUFG
      port map (
	  			O => clkdv_i,
	  			I => clkdv_int
				);


  BUFG_CLKFX : BUFG
      port map (
	  			O => clkfx_i,
	  			I => clkfx_int
				);

      clk0_out <= clk0_i;      
      clkdv_out <= clkdv_i;
      clkfx_out <= clkfx_i;

end architecture dcm_ip_arch;