LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST IS 
	port (FSIN : IN STD_LOGIC;
		  CLK : IN STD_LOGIC;
		  DOUT : OUT STD_LOGIC_VECTOR(31 downto 0));
END FREQTEST;
ARCHITECTURE struc OF FREQTEST IS
component HUO
PORT(CLR11:IN STD_LOGIC;
     CARRY_OUT11:IN STD_LOGIC;
     CLRR:OUT STD_LOGIC);
 end component;
component FTCTRL
	PORT(CLK : IN STD_LOGIC;
		 TSTEN : OUT STD_LOGIC;
		 CLR_CNT : OUT STD_LOGIC;
		 LOAD : OUT STD_LOGIC);
end component;
component COUNTER32B
	PORT(CLK : IN STD_LOGIC;
		 CLR : IN STD_LOGIC;
		 ENA : IN STD_LOGIC;
		 CARRY_OUT : OUT STD_LOGIC;
		 CQ : OUT STD_LOGIC_VECTOR(3 downto 0));
end component;
component REG32B
	PORT(LOAD : IN STD_LOGIC;
		 DIN : IN STD_LOGIC_VECTOR(31 downto 0);
		 DOUT : OUT STD_LOGIC_VECTOR(31 downto 0));
end component;
  signal Load1,TSTEN1,CLR_CNT1,CLR_CNT2: STD_LOGIC;
  signal DTO1 : STD_LOGIC_VECTOR(31 downto 0);
  signal CARRY_OUT1 : STD_LOGIC_VECTOR(7 downto 0);
BEGIN 
U1 : FTCTRL
PORT MAP(CLK => CLK,
		 TSTEN => TSTEN1,
		 CLR_CNT => CLR_CNT1,
		 LOAD => Load1);
U2 : REG32B
PORT MAP(LOAD => Load1,
		 DIN => DTO1,
		 DOUT => DOUT);
U3 : HUO
PORT MAP(CLR11 => CLR_CNT1,
         CARRY_OUT11 => CARRY_OUT1(7),
         CLRR => CLR_CNT2);
U4 : COUNTER32B
PORT MAP(CLK => FSIN,
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(3 downto 0),
         CARRY_OUT => CARRY_OUT1(0));     
U5 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(0),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(7 downto 4),
         CARRY_OUT => CARRY_OUT1(1));
U6 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(1),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(11 downto 8),
         CARRY_OUT => CARRY_OUT1(2));
U7 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(2),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(15 downto 12),
         CARRY_OUT => CARRY_OUT1(3));
U8 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(3),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(19 downto 16),
         CARRY_OUT => CARRY_OUT1(4));
U9 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(4),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(23 downto 20),
         CARRY_OUT => CARRY_OUT1(5));
U10 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(5),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(27 downto 24),
         CARRY_OUT => CARRY_OUT1(6));
U11 : COUNTER32B
PORT MAP(CLK => CARRY_OUT1(6),
		 CLR => CLR_CNT2,
		 ENA => TSTEN1,
		 CQ => DTO1(31 downto 28),
         CARRY_OUT => CARRY_OUT1(7));
END struc;