?? reg32b.rpt
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Project Information e:\eda\edakechengsheji\reg32b.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/19/2008 13:30:52
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
REG32B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
reg32b EP1K10TC100-1 33 32 0 0 0 % 32 5 %
User Pins: 33 32 0
Project Information e:\eda\edakechengsheji\reg32b.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K10TC100-1 are preliminary
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
***** Logic for device 'reg32b' compiled without errors.
Device: EP1K10TC100-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** ERROR SUMMARY **
Info: Chip 'reg32b' in device 'EP1K10TC100-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R
E
D D D V S D D ^
O D D O O D C D D E O V D O D D D D D
# U I I U U I C D D D I I R U C I U I O I O A
T T N N T G T N I I I I G N N V T C N T N U N U T
C 1 2 1 2 N 1 2 N N N N N 2 2 E 2 I 1 3 1 T 1 T A
K 3 7 8 2 D 2 3 T 3 4 2 D 8 5 D 5 O 5 0 6 2 1 7 0
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
^CONF_DONE | 1 75 | ^DCLK
^nCEO | 2 74 | ^nCE
#TDO | 3 73 | #TDI
VCCIO | 4 72 | VCCINT
DOUT23 | 5 71 | DOUT16
DOUT26 | 6 70 | DOUT10
DIN7 | 7 69 | DOUT28
DOUT14 | 8 68 | DIN31
DIN21 | 9 67 | VCCIO
DOUT1 | 10 66 | GND
GND | 11 65 | DIN30
VCCINT | 12 64 | DOUT9
DOUT27 | 13 EP1K10TC100-1 63 | DOUT11
DOUT5 | 14 62 | DOUT19
DIN29 | 15 61 | DIN9
DOUT29 | 16 60 | VCCINT
VCCIO | 17 59 | GND
GND | 18 58 | DOUT17
DOUT18 | 19 57 | DOUT20
DOUT4 | 20 56 | DIN22
DIN6 | 21 55 | DIN20
DOUT24 | 22 54 | ^MSEL0
DOUT6 | 23 53 | ^MSEL1
#TMS | 24 52 | VCCINT
^nSTATUS | 25 51 | ^nCONFIG
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
D D D D D D D D D V G V D L D G G D V D D D D D D
O I I I I I O I I C N C I O I N N I C O I I O O O
U N N N N N U N N C D C N A N D D N C U N N U U U
T 2 5 1 2 8 T 1 1 I _ 0 D 1 _ 1 I T 1 1 T T T
2 4 4 6 8 3 2 N C C 0 O 3 9 7 1 3 0
1 T K K 5 1
L L
K K
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
A2 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A24 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B11 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 59/60 ( 98%)
Total logic cells used: 32/576 ( 5%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 32/2304 ( 1%)
Total input pins required: 33
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 32
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 2 12/0
B: 1 0 1 0 1 0 0 1 0 0 2 0 0 1 0 0 0 0 0 1 0 0 0 0 1 9/0
C: 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 11/0
Total: 4 2 1 0 2 1 1 2 0 1 2 0 0 2 0 2 1 1 2 1 1 1 1 0 4 32/0
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - - -- INPUT ^ 0 0 0 1 DIN0
40 - - - -- INPUT ^ 0 0 0 1 DIN1
89 - - - -- INPUT ^ 0 0 0 1 DIN2
91 - - - -- INPUT ^ 0 0 0 1 DIN3
90 - - - -- INPUT ^ 0 0 0 1 DIN4
28 - - - 20 INPUT ^ 0 0 0 1 DIN5
21 - - C -- INPUT ^ 0 0 0 1 DIN6
7 - - A -- INPUT ^ 0 0 0 1 DIN7
31 - - - 17 INPUT ^ 0 0 0 1 DIN8
61 - - B -- INPUT ^ 0 0 0 1 DIN9
43 - - - 12 INPUT ^ 0 0 0 1 DIN10
78 - - - 01 INPUT ^ 0 0 0 1 DIN11
34 - - - 14 INPUT ^ 0 0 0 1 DIN12
33 - - - 15 INPUT ^ 0 0 0 1 DIN13
29 - - - 19 INPUT ^ 0 0 0 1 DIN14
82 - - - 04 INPUT ^ 0 0 0 1 DIN15
80 - - - 03 INPUT ^ 0 0 0 1 DIN16
47 - - - 09 INPUT ^ 0 0 0 1 DIN17
97 - - - 23 INPUT ^ 0 0 0 1 DIN18
46 - - - 10 INPUT ^ 0 0 0 1 DIN19
55 - - C -- INPUT ^ 0 0 0 1 DIN20
9 - - A -- INPUT ^ 0 0 0 1 DIN21
56 - - C -- INPUT ^ 0 0 0 1 DIN22
93 - - - 13 INPUT ^ 0 0 0 1 DIN23
27 - - - 21 INPUT ^ 0 0 0 1 DIN24
86 - - - 09 INPUT ^ 0 0 0 1 DIN25
30 - - - 18 INPUT ^ 0 0 0 1 DIN26
98 - - - 24 INPUT ^ 0 0 0 1 DIN27
87 - - - 12 INPUT ^ 0 0 0 1 DIN28
15 - - B -- INPUT ^ 0 0 0 1 DIN29
65 - - B -- INPUT ^ 0 0 0 1 DIN30
68 - - A -- INPUT ^ 0 0 0 1 DIN31
39 - - - -- INPUT G ^ 0 0 0 0 LOAD
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
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