?? reg32b.rpt
字號:
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
50 - - - 02 OUTPUT 0 1 0 0 DOUT0
10 - - A -- OUTPUT 0 1 0 0 DOUT1
79 - - - 02 OUTPUT 0 1 0 0 DOUT2
45 - - - 11 OUTPUT 0 1 0 0 DOUT3
20 - - C -- OUTPUT 0 1 0 0 DOUT4
14 - - B -- OUTPUT 0 1 0 0 DOUT5
23 - - C -- OUTPUT 0 1 0 0 DOUT6
77 - - - 01 OUTPUT 0 1 0 0 DOUT7
32 - - - 16 OUTPUT 0 1 0 0 DOUT8
64 - - B -- OUTPUT 0 1 0 0 DOUT9
70 - - A -- OUTPUT 0 1 0 0 DOUT10
63 - - B -- OUTPUT 0 1 0 0 DOUT11
94 - - - 19 OUTPUT 0 1 0 0 DOUT12
99 - - - 24 OUTPUT 0 1 0 0 DOUT13
8 - - A -- OUTPUT 0 1 0 0 DOUT14
48 - - - 07 OUTPUT 0 1 0 0 DOUT15
71 - - A -- OUTPUT 0 1 0 0 DOUT16
58 - - C -- OUTPUT 0 1 0 0 DOUT17
19 - - C -- OUTPUT 0 1 0 0 DOUT18
62 - - B -- OUTPUT 0 1 0 0 DOUT19
57 - - C -- OUTPUT 0 1 0 0 DOUT20
26 - - - 23 OUTPUT 0 1 0 0 DOUT21
96 - - - 22 OUTPUT 0 1 0 0 DOUT22
5 - - A -- OUTPUT 0 1 0 0 DOUT23
22 - - C -- OUTPUT 0 1 0 0 DOUT24
84 - - - 05 OUTPUT 0 1 0 0 DOUT25
6 - - A -- OUTPUT 0 1 0 0 DOUT26
13 - - B -- OUTPUT 0 1 0 0 DOUT27
69 - - A -- OUTPUT 0 1 0 0 DOUT28
16 - - B -- OUTPUT 0 1 0 0 DOUT29
81 - - - 03 OUTPUT 0 1 0 0 DOUT30
49 - - - 06 OUTPUT 0 1 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 05 DFFE + 1 0 1 0 :34
- 4 - B 03 DFFE + 1 0 1 0 :36
- 7 - B 19 DFFE + 1 0 1 0 :38
- 5 - A 01 DFFE + 1 0 1 0 :40
- 1 - B 24 DFFE + 1 0 1 0 :42
- 2 - A 21 DFFE + 1 0 1 0 :44
- 2 - C 06 DFFE + 1 0 1 0 :46
- 8 - C 18 DFFE + 1 0 1 0 :48
- 1 - A 17 DFFE + 1 0 1 0 :50
- 1 - C 22 DFFE + 1 0 1 0 :52
- 2 - A 24 DFFE + 1 0 1 0 :54
- 2 - C 10 DFFE + 1 0 1 0 :56
- 6 - B 05 DFFE + 1 0 1 0 :58
- 1 - C 15 DFFE + 1 0 1 0 :60
- 1 - C 07 DFFE + 1 0 1 0 :62
- 1 - A 01 DFFE + 1 0 1 0 :64
- 2 - C 08 DFFE + 1 0 1 0 :66
- 8 - A 18 DFFE + 1 0 1 0 :68
- 1 - C 24 DFFE + 1 0 1 0 :70
- 2 - C 20 DFFE + 1 0 1 0 :72
- 4 - B 11 DFFE + 1 0 1 0 :74
- 2 - A 02 DFFE + 1 0 1 0 :76
- 2 - B 08 DFFE + 1 0 1 0 :78
- 1 - A 15 DFFE + 1 0 1 0 :80
- 4 - A 01 DFFE + 1 0 1 0 :82
- 7 - C 13 DFFE + 1 0 1 0 :84
- 3 - B 13 DFFE + 1 0 1 0 :86
- 1 - C 16 DFFE + 1 0 1 0 :88
- 2 - B 11 DFFE + 1 0 1 0 :90
- 4 - A 02 DFFE + 1 0 1 0 :92
- 8 - A 24 DFFE + 1 0 1 0 :94
- 1 - B 01 DFFE + 1 0 1 0 :96
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 4/ 48( 8%) 7/ 48( 14%) 3/16( 18%) 7/16( 43%) 0/16( 0%)
B: 5/ 96( 5%) 4/ 48( 8%) 4/ 48( 8%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 4/ 96( 4%) 4/ 48( 8%) 8/ 48( 16%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 LOAD
Device-Specific Information: e:\eda\edakechengsheji\reg32b.rpt
reg32b
** EQUATIONS **
DIN0 : INPUT;
DIN1 : INPUT;
DIN2 : INPUT;
DIN3 : INPUT;
DIN4 : INPUT;
DIN5 : INPUT;
DIN6 : INPUT;
DIN7 : INPUT;
DIN8 : INPUT;
DIN9 : INPUT;
DIN10 : INPUT;
DIN11 : INPUT;
DIN12 : INPUT;
DIN13 : INPUT;
DIN14 : INPUT;
DIN15 : INPUT;
DIN16 : INPUT;
DIN17 : INPUT;
DIN18 : INPUT;
DIN19 : INPUT;
DIN20 : INPUT;
DIN21 : INPUT;
DIN22 : INPUT;
DIN23 : INPUT;
DIN24 : INPUT;
DIN25 : INPUT;
DIN26 : INPUT;
DIN27 : INPUT;
DIN28 : INPUT;
DIN29 : INPUT;
DIN30 : INPUT;
DIN31 : INPUT;
LOAD : INPUT;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC1_B1;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC8_A24;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC4_A2;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC2_B11;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = _LC1_C16;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = _LC3_B13;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = _LC7_C13;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = _LC4_A1;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = _LC1_A15;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = _LC2_B8;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = _LC2_A2;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = _LC4_B11;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = _LC2_C20;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = _LC1_C24;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = _LC8_A18;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = _LC2_C8;
-- Node name is 'DOUT16'
-- Equation name is 'DOUT16', type is output
-- Node name is 'DOUT17'
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