/* system.h * * Machine generated for a CPU named "cpu_0" as defined in: * H:\Q51\alltest_c20\software\ALL_TEST_syslib\..\..\Nios.ptf * * Generated: 2008-09-27 15:07:36.406 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "Nios"#define ALT_CPU_NAME "cpu_0"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONE"#define ALTERA_NIOS_DEV_BOARD_CYCLONE_2C35#define ALT_STDIN "/dev/uart_0"#define ALT_STDOUT "/dev/uart_0"#define ALT_STDERR "/dev/uart_0"#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "small"#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 0#define NIOS2_DCACHE_LINE_SIZE_LOG2 0#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x01000020#define NIOS2_RESET_ADDR 0x00000000#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __LCD_TRI_1602#define __LCD_TRI_12864#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_DM9000#define __ALTERA_AVALON_PIO#define __SRAM_256X32BIT#define __PS2#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ADS7822#define __OC_I2C_MASTER#define __SEG78LED#define __ALTERA_AVALON_SYSID#define __ALTERA_AVALON_UART#define __ALTERA_AVALON_TIMER#define __ALTERA_AVALON_SPI#define __USB_PORT/* * tri_state_bridge_0 configuration * */#define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"#define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"/* * lcd_tri_1602 configuration * */#define LCD_TRI_1602_NAME "/dev/lcd_tri_1602"#define LCD_TRI_1602_TYPE "lcd_tri_1602"#define LCD_TRI_1602_BASE 0x00800020#define LCD_TRI_1602_SPAN 16#define LCD_TRI_1602_HDL_PARAMETERS ""/* * lcd_tri_12864 configuration * */#define LCD_TRI_12864_NAME "/dev/lcd_tri_12864"#define LCD_TRI_12864_TYPE "lcd_tri_12864"#define LCD_TRI_12864_BASE 0x00800030#define LCD_TRI_12864_SPAN 16#define LCD_TRI_12864_HDL_PARAMETERS ""/* * cfi_flash_0 configuration * */#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"#define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"#define CFI_FLASH_0_BASE 0x00000000#define CFI_FLASH_0_SPAN 8388608#define CFI_FLASH_0_SETUP_VALUE 40#define CFI_FLASH_0_WAIT_VALUE 160#define CFI_FLASH_0_HOLD_VALUE 40#define CFI_FLASH_0_TIMING_UNITS "ns"#define CFI_FLASH_0_UNIT_MULTIPLIER 1#define CFI_FLASH_0_SIZE 8388608/* * dm9000 configuration * */#define DM9000_NAME "/dev/dm9000"#define DM9000_TYPE "altera_avalon_dm9000"#define DM9000_BASE 0x00800000#define DM9000_SPAN 32#define DM9000_IRQ 0#define DM9000_IS_ETHERNET_MAC 1#define DM9000_DM9000_REGISTERS_OFFSET 0x0000#define DM9000_DM9000_DATA_BUS_WIDTH 16/* * DM9000_RST configuration * */#define DM9000_RST_NAME "/dev/DM9000_RST"#define DM9000_RST_TYPE "altera_avalon_pio"#define DM9000_RST_BASE 0x00800120#define DM9000_RST_SPAN 16#define DM9000_RST_DO_TEST_BENCH_WIRING 0#define DM9000_RST_DRIVEN_SIM_VALUE 0x0000#define DM9000_RST_HAS_TRI 0#define DM9000_RST_HAS_OUT 1#define DM9000_RST_HAS_IN 0#define DM9000_RST_CAPTURE 0#define DM9000_RST_EDGE_TYPE "NONE"#define DM9000_RST_IRQ_TYPE "NONE"#define DM9000_RST_FREQ 50000000/* * tri_state_bridge_1 configuration * */#define TRI_STATE_BRIDGE_1_NAME "/dev/tri_state_bridge_1"#define TRI_STATE_BRIDGE_1_TYPE "altera_avalon_tri_state_bridge"/* * sram_256x32bit_0 configuration * */#define SRAM_256X32BIT_0_NAME "/dev/sram_256x32bit_0"#define SRAM_256X32BIT_0_TYPE "sram_256x32bit"#define SRAM_256X32BIT_0_BASE 0x00900000#define SRAM_256X32BIT_0_SPAN 1048576#define SRAM_256X32BIT_0_HDL_PARAMETERS ""/* * ps2_0 configuration * */#define PS2_0_NAME "/dev/ps2_0"#define PS2_0_TYPE "ps2"#define PS2_0_BASE 0x008001D8#define PS2_0_SPAN 2#define PS2_0_IRQ 1#define PS2_0_HDL_PARAMETERS ""/* * jtag_uart_0 configuration * */#define JTAG_UART_0_NAME "/dev/jtag_uart_0"#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_0_BASE 0x008001C0#define JTAG_UART_0_SPAN 8#define JTAG_UART_0_IRQ 2#define JTAG_UART_0_WRITE_DEPTH 64#define JTAG_UART_0_READ_DEPTH 64#define JTAG_UART_0_WRITE_THRESHOLD 8#define JTAG_UART_0_READ_THRESHOLD 8#define JTAG_UART_0_READ_CHAR_STREAM ""#define JTAG_UART_0_SHOWASCII 1#define JTAG_UART_0_READ_LE 0#define JTAG_UART_0_WRITE_LE 0#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0/* * sdram_0 configuration * */#define SDRAM_0_NAME "/dev/sdram_0"#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"#define SDRAM_0_BASE 0x01000000#define SDRAM_0_SPAN 16777216#define SDRAM_0_REGISTER_DATA_IN 1#define SDRAM_0_SIM_MODEL_BASE 1#define SDRAM_0_SDRAM_DATA_WIDTH 32#define SDRAM_0_SDRAM_ADDR_WIDTH 12#define SDRAM_0_SDRAM_ROW_WIDTH 12#define SDRAM_0_SDRAM_COL_WIDTH 8#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1#define SDRAM_0_SDRAM_NUM_BANKS 4#define SDRAM_0_REFRESH_PERIOD 15.625#define SDRAM_0_POWERUP_DELAY 100#define SDRAM_0_CAS_LATENCY 3#define SDRAM_0_T_RFC 70#define SDRAM_0_T_RP 20#define SDRAM_0_T_MRD 3#define SDRAM_0_T_RCD 20#define SDRAM_0_T_AC 5.5#define SDRAM_0_T_WR 14#define SDRAM_0_INIT_REFRESH_COMMANDS 2#define SDRAM_0_INIT_NOP_DELAY 0#define SDRAM_0_SHARED_DATA 0#define SDRAM_0_STARVATION_INDICATOR 0#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""#define SDRAM_0_IS_INITIALIZED 1#define SDRAM_0_SDRAM_BANK_WIDTH 2/* * ads7822_0 configuration * */#define ADS7822_0_NAME "/dev/ads7822_0"#define ADS7822_0_TYPE "ads7822"#define ADS7822_0_BASE 0x008001DA#define ADS7822_0_SPAN 2#define ADS7822_0_IRQ 3/* * oc_i2c_master_0 configuration * */#define OC_I2C_MASTER_0_NAME "/dev/oc_i2c_master_0"#define OC_I2C_MASTER_0_TYPE "oc_i2c_master"#define OC_I2C_MASTER_0_BASE 0x00800080#define OC_I2C_MASTER_0_SPAN 32#define OC_I2C_MASTER_0_IRQ 4/* * seg78led_0 configuration * */#define SEG78LED_0_NAME "/dev/seg78led_0"#define SEG78LED_0_TYPE "seg78led"#define SEG78LED_0_BASE 0x008001C8#define SEG78LED_0_SPAN 8#define SEG78LED_0_HDL_PARAMETERS ""