package defcon is
constant sreg_width :integer:=20;
end defcon;
use work.defcon.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sreg1 is
port(sl,se,clk:in std_logic;
	datain:in std_logic_vector(sreg_width-1 downto 0);
	q:out std_logic);
end sreg1;
architecture behav of sreg1 is
signal tmpreg:std_logic_vector(sreg_width-1 downto 0);
begin
q<=tmpreg(sreg_width-1);
process(sl,clk)
begin
		if(clk'event and clk='1')then
			if(sl='0')then
				tmpreg<=datain;
			else				
				for i in sreg_width-1 downto 1 loop
					tmpreg(i)<=tmpreg(i-1);
				end loop;
				tmpreg(0)<=se;				
			end if;
		end if;
end process;
end behav;