module gps_jiance (clk,Gclk,right,alarm,a,b);
input       clk,Gclk;
//output[21:0]    cnt1,cnt2;
reg         Gclk1,Gclk2;
reg [21:0]      cnt1,cnt2,cnt;//Cnt2為脈寬檢測 cnt1為秒脈沖檢測
output      right,alarm,a,b;
reg         right,alarm,a,b;  
always @ (posedge clk ) 
      begin
       Gclk1<=Gclk;
       Gclk2<=Gclk1;
      end
always @ (posedge clk ) 
     begin
       if(!Gclk2 && Gclk1)
           cnt1<='b0;   
       else     cnt1<=cnt1+1;
     end
always @ (posedge clk ) 
      begin
       if(Gclk)
            cnt2<=cnt2+1;      
       else   cnt2<='b0; 
      end
always @ (negedge Gclk ) 
      begin
       //if  ( cnt2>=40) 
          if  ( cnt2>=5) 
             a<='b1; 
        else a<='b0;     
      end
always @ (posedge Gclk ) 
      begin
         if (a==1)
          begin
         // if  ( cnt1<=4001000 && cnt1>=3999000)
             if  ( cnt1<=12 && cnt1>=8) 
                cnt<=cnt+1;
           else cnt<='b0; 
          end
         else  cnt<='b0;   
      end
always @ (posedge clk )
    begin 
       //if(cnt1<=4001000)
       if(cnt1<=12)
       begin if (cnt>=2) 
                 begin  
                     right<=1'b1;alarm<=1'b0;b<=Gclk;
                 end
             else  begin   right<=1'b0;alarm<=1'b1;b<=1'b0; end
       end  
     else  begin   right<=1'b0;alarm<=1'b1;b<=1'b0; end
    end
endmodule
/*module gps_jiance (clk,Gclk,flag1,flag2,cnt1,cnt2,a);
input           clk,Gclk;
output[3:0]    cnt1,cnt2;
reg             Gclk1,Gclk2;
reg [3:0]      cnt1,cnt2;//
output         flag1,flag2,a;
reg            flag1,flag2,a,flag;  
reg [2:0]    current_state,next_state;//  
parameter   s0=0,s1=1, s2=2, s3=3, s4=4, s5=5;//, s6=3'b110;
initial begin cnt1<=0;cnt2<=0;flag1=0;flag2=0;end
always @ (posedge clk ) 
     begin
       if(Gclk)
              cnt2<=cnt2+1;      
       else cnt2<='b0;
      end
always @ (posedge clk ) 
      begin
       Gclk1<=Gclk;
       Gclk2<=Gclk1;
      end
always @ (posedge clk ) 
     begin
       if(!Gclk2 && Gclk1)
            cnt1<='b0;  
       else     
             cnt1<=cnt1+1;
    end
always @ (posedge clk )
   begin
     case (current_state) 
         s0:  begin
                   if (!Gclk2 && Gclk1) 
                       current_state= s1; 
                   else  current_state= s0;
                         
              end
         s1:  begin   // if(a)
                  if(!Gclk)
                    begin
                    if (cnt2>=4 )  
                            current_state= s2;
                       else   current_state=s0 ;
                    end     
                  else    current_state=s1 ;
              end
         s2:  begin   
                 //if (cnt<=4000008 && cnt>=3999992) 
                if      (cnt1>=8 && cnt1<=12&& Gclk) 
                           current_state=s3 ;
                else    current_state=s2;
             end

         s3:  begin 
                      //if (cnt<=4000008 && cnt>=3999992) 
                     if (cnt1>=8 && cnt1<=12&& Gclk)
                            current_state=s4 ;
                     else    current_state=s3;
              end 
         s4:  begin 
                      //if (cnt<=4000008 && cnt>=3999992) 
                     if (cnt1>=8 && cnt1<=12&& Gclk)
                            current_state=s4 ;
                     else    current_state=s4;
              end 
      
         default:   current_state=s1;
         endcase
   end
always @ (current_state )
   begin
     case (current_state) 
         s0:       begin    flag1<=1'b0;flag2<=1'b1;   end
         //s1:       begin    flag1<=1'b0;flag2<=1'b1;   end
         s1:       begin    flag1<=1'b0;flag2<=1'b1;   end   
         s2:       begin    flag1<=1'b0;flag2<=1'b1;   end
         s3:       begin    flag1<=1'b1;flag2<=1'b0;   end
         s4:       begin    flag1<=1'b1;flag2<=1'b0;   end
        // s5:       begin    flag1<=1'b1;flag2<=1'b0;   end
         default:  begin    flag1<=1'b0;flag2<=1'b1;   end
    endcase
   end
endmodule*/