?? k9g8g08.c
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U32 block,page;
//U8 buffer[512+16];
U8 buffer[2048+64];
//printf("\n[SMC(K9g8g08) NAND Flash block read]\n");
printf("\n[SMC(K9G8G08 or K9LAG08) NAND Flash block read]\n");
NF_Init();
id=NF_CheckId();
printf("ID=%x(0xecxx)\n",id);
//if((id!=0xecdc)&&(id!=0xecd3)) // msp4
if((id!=0xecdc)&&(id!=0xecd5)) // msp4
return;
printf("Input target block number:");
scanf("%d",&block);
printf("Input target page number:");
scanf("%d",&page);
NF_ReadPage(block,page,buffer,buffer+2048);
printf("\nblock=%d, page=%d \n\nData Area",block,page);
for(i=0;i<2048;i++)
{
if(i%16==0)
printf("\n%3xh : ",i);
printf("%02x ",buffer[i]);
}
printf("\n\nSpare Area",i);
for(i=2048;i<2048+64;i++)
{
if(i%16==0)
printf("\n%3xh : ",i-2048);
printf("%02x ",buffer[i]);
}
printf("\n\n");
}
//*************************************************
//*************************************************
//** H/W dependent functions **
//*************************************************
//*************************************************
// NAND Flash Memory Commands
#define SEQ_DATA_INPUT (0x80)
#define READ_ID (0x90)
#define RESET (0xFF)
#define READ_1_1 (0x00)
#define READ_1_2 (0x01)
#define READ_2 (0x50)
#define PAGE_PROGRAM (0x10)
#define BLOCK_ERASE (0x60)
#define BLOCK_ERASE_CONFIRM (0xD0)
#define READ_STATUS (0x70)
// block0: reserved for boot strap
// block1~4095: used for OS image
// badblock SE: xx xx xx xx xx 00 ....
// good block SE: ECC0 ECC1 ECC2 FF FF FF ....
#define WRITEVERIFY (0) //verifing is enable at writing.
/*
#define NF_CMD(cmd) {rNFCMD=cmd;}
#define NF_ADDR(addr) {rNFADDR=addr;}
#define NF_Xm0CSn2_OUT_L() {rNFCONF&=~(1<<11);}
#define NF_Xm0CSn2_OUT_H() {rNFCONF|=(1<<11);}
#define NF_RSTECC() {rNFCONF|=(1<<12);}
#define NF_RDDATA() (rNFDATA)
#define NF_WRDATA(data) {rNFDATA=data;}
#define NF_WAITRB() {while(!(rNFSTAT&(1<<0)));}
//wait tWB and check F_RNB pin.
*/
//#define ID_K9g8g08V0M 0xeca1 // msp3
#define ID_K9g8g08V0M 0xecaa // msp4
static U8 seBuf[64]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
// 1block=(2048+64)bytes x 64pages
// 1024block
// A[23:14][13:9]
// block page
static int NF_EraseBlock(U32 block)
{
U32 blockPage=(block<<7);
//U32 blockPage=(block<<8);
#if BAD_CHECK
if(NF_IsBadBlock(block) && block!=0) //block #0 can't be bad block for NAND boot
return 0;
#endif
NF_Xm0CSn2_OUT_L();
NF_CMD(0x60); // Erase one block 1st command
NF_ADDR(blockPage&0xff); // Page number=A[7:0]=0
NF_ADDR((blockPage>>8)&0xff); // Page number=A[11:8]=0
NF_ADDR((blockPage>>16)&0xff); // Page number=A[11:8]=0
//NF_ADDR((blockPage>>16)&0xff);
//NF_ADDR((blockPage>>24)&0xff);
NF_CMD(0xd0); // Erase one blcok 2nd command
Delay(1); //wait tWB(100ns)
//NF_WAITRB(); // Wait tBERS max 3ms.
NF_CMD(0x70); // Read status command
if (NF_RDDATA()&0x1) // Erase error
{
NF_Xm0CSn2_OUT_H();
printf("[ERASE_ERROR:block#=%d]\n",block);
NF_MarkBadBlock(block);
return 0;
}
else
{
NF_Xm0CSn2_OUT_H();
return 1;
}
}
static int NF_IsBadBlock(U32 block)
{
unsigned int blockPage, page = 127;
U8 data;
blockPage=(block<<7) + page; // page(0 ~ 127), bad block mark in 127 page
NF_Xm0CSn2_OUT_L();
//NF_CMD(0x50); // Spare array read command
NF_CMD(0x0); // read command
NF_ADDR((2048+0) & 0xf); //
NF_ADDR(((2048+0)>>8) & 0xff); //
NF_ADDR((blockPage) & 0xff); //
NF_ADDR((blockPage>>8)&0xff); //
NF_ADDR((blockPage>>16)&0xff); // msp4 2006.09.27
NF_CMD(0x30); // read command
Delay(1); // wait tWB(100ns)
NF_WAITRB(); // Wait tR(max 12us)
data=NF_RDDATA();
NF_Xm0CSn2_OUT_H();
if(data!=0xff)
{
printf("[block %d:bad block(%x)]\n",block,data);
return 1;
}
else
{
printf(".");
return 0;
}
}
static int NF_MarkBadBlock(U32 block)
{
int i, page = 127;
U32 blockPage=(block<<7) + page; // page(0 ~ 127), bad block mark in 255 page
seBuf[0]=0x44;
seBuf[1]=0xff;
seBuf[2]=0xff;
seBuf[5]=0xff; // Bad blcok mark=0
NF_Xm0CSn2_OUT_L();
//NF_CMD(0x50);
NF_CMD(0x80); // Write 1st command
NF_ADDR((2048+0) & 0xff); // The mark of bad block is
NF_ADDR(((2048+0)>>8) & 0xff); // marked 5th spare array
NF_ADDR(blockPage & 0xff); // in the 1st page.
NF_ADDR((blockPage>>8) & 0xff);
NF_ADDR((blockPage>>16) & 0xff); // msp4 2006.09.27
for(i=0;i<64;i++)
{
NF_WRDATA(seBuf[i]); // Write spare array
}
NF_CMD(0x10); // Write 2nd command
Delay(1); //tWB = 100ns.
NF_WAITRB(); // Wait tPROG(200~500us)
NF_CMD(0x70);
Delay(1); //twhr=60ns//
if (NF_RDDATA()&0x1) // Spare arrray write error
{
NF_Xm0CSn2_OUT_H();
printf("[Program error is occurred but ignored]\n");
}
else
{
NF_Xm0CSn2_OUT_H();
}
printf("[block #%d is marked as a bad block]\n",block);
return 1;
}
static int NF_ReadPage(U32 block,U32 page,U8 *buffer,U8 *spareBuf)
{
int i;
unsigned int blockPage;
U8 *bufPt=buffer;
page=page&0x7f;
blockPage=(block<<7)+page;
NF_Xm0CSn2_OUT_L();
NF_CMD(0x00); // 1st Read command
NF_ADDR(0); // Column A[7:0]= 0
NF_ADDR(0); // Column A[11:8] = 0
NF_ADDR(blockPage & 0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[28:x] msp4 2006/09/27
NF_CMD(0x30); // 2nd Read command
Delay(1); //wait tWB(100ns)/////??????
NF_WAITRB(); // Wait tR(max 12us)
for(i=0;i<(2048);i++)
{
*bufPt++=NF_RDDATA(); // Read one page
}
if(spareBuf!=NULL)
{
for(i=0;i<64;i++)
spareBuf[i]=NF_RDDATA(); // Read spare array
}
NF_Xm0CSn2_OUT_H();
return 1;
}
static int NF_WritePage(U32 block,U32 page,U8 *buffer,U8 *spareBuf)
{
int i;
U32 blockPage=(block<<7)+page;
U8 *bufPt=buffer;
NF_Xm0CSn2_OUT_L();
NF_CMD(0x0);
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column A[7:0]=0
NF_ADDR(0); // Column A[11:8]=0
NF_ADDR(blockPage&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20] // msp3
NF_ADDR((blockPage>>16)&0xff); // A[28:x] // msp4 // 2006.09.27
for(i=0;i<2048;i++)
{
NF_WRDATA(*bufPt++); // Write one page to NFM from buffer
}
if(spareBuf!=NULL)
{
for(i=0;i<64;i++)
{
NF_WRDATA(spareBuf[i]); // Write spare array(ECC and Mark)
}
}
NF_CMD(0x10); // Write 2nd command
Delay(1); //tWB = 100ns.
NF_WAITRB(); //wait tPROG 200~500us;
NF_CMD(0x70); // Read status command
Delay(1); //twhr=60ns
if (NF_RDDATA()&0x1) // Page write error
{
NF_Xm0CSn2_OUT_H();
printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF_MarkBadBlock(block);
return 0;
}
else
{
NF_Xm0CSn2_OUT_H();
#if (WRITEVERIFY==1)
//return NF_VerifyPage(block,page,pPage);
#else
return 1;
#endif
}
}
static int NF_2Plane_WritePage(U32 block,U32 page,U8 *buffer,U8 *spareBuf,U8 *spareBuf2)
{
int i;
U32 blockPage = (block<<8)+page;
U32 blockPage2nd = (block<<8)+(page+128);
U8 *bufPt=buffer;
NF_Xm0CSn2_OUT_L();
NF_CMD(0x0);
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column A[7:0]=0
NF_ADDR(0); // Column A[11:8]=0
NF_ADDR(blockPage&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20] // msp3
NF_ADDR((blockPage>>16)&0xff); // A[28:x] // msp4 // 2006.09.27
for(i=0;i<2048;i++)
NF_WRDATA(*bufPt++); // Write one page to NFM from buffer
if(spareBuf!=NULL)
for(i=0;i<64;i++)
NF_WRDATA(spareBuf[i]); // Write spare array(ECC and Mark)
NF_CMD(0x11); // Program command (dummy)
Delay(10); //tDBSY = 1uS
// NF_Xm0CSn2_OUT_L();
// NF_CMD(0x0);
NF_CMD(0x81); // Write 2nd command
NF_ADDR(0); // Column A[7:0]=0
NF_ADDR(0); // Column A[11:8]=0
NF_ADDR(blockPage2nd&0xff); // A[19:12]
NF_ADDR((blockPage2nd>>8)&0xff); // A[27:20] // msp3
NF_ADDR((blockPage2nd>>16)&0xff); // A[28:x] // msp4 // 2006.09.27
for(i=0;i<2048;i++)
NF_WRDATA(*bufPt++); // Write one page to NFM from buffer
if(spareBuf2!=NULL)
for(i=0;i<64;i++)
NF_WRDATA(spareBuf2[i]); // Write spare array(ECC and Mark)
NF_CMD(0x10); // Program confirm command (true)
Delay(1); //tWB = 100ns.
NF_WAITRB(); //wait tPROG 200~500us;
NF_CMD(0x70); // Read status command
Delay(1); //twhr=60ns
if (NF_RDDATA()&0x1) // Page write error
{
NF_Xm0CSn2_OUT_H();
printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF_MarkBadBlock(block);
return 0;
}
else
{
NF_Xm0CSn2_OUT_H();
#if (WRITEVERIFY==1)
//return NF_VerifyPage(block,page,pPage);
#else
return 1;
#endif
}
}
static U16 NF_CheckId(void)
{
U16 id;
NF_Xm0CSn2_OUT_L();
NF_CMD(0x90);
NF_ADDR(0x0);
Delay(1); //wait tWB(100ns)
id=NF_RDDATA()<<8; // Maker code(K9f1g08V:0xec)
id|=NF_RDDATA(); // Devide code(K9f1g08V:0x76)
NF_Xm0CSn2_OUT_H();
return id;
}
static void NF_Reset(void)
{
NF_Xm0CSn2_OUT_L();
NF_CMD(0xFF); //reset command
Delay(1); //tWB = 100ns.
NF_WAITRB(); //wait 200~500us;
NF_Xm0CSn2_OUT_H();
}
static void NF_Init(void)
{
NF_Reset();
//NF_Xm0CSn2_OUT_L();
NF_CMD(READ_1_1);
//NF_Xm0CSn2_OUT_H();
}
//*************************************************
//*************************************************
//** JTAG dependent primitive functions **
//*************************************************
//*************************************************
void K9g8g08_JtagInit(void)
{
JTAG_RunTestldleState();
JTAG_ShiftIRState(EXTEST);
//Added to SJF2440
S6410_SetPin(Xm0RDY1_CLE_CON,LOW);
S6410_SetPin(Xm0RDY0_ALE_CON,LOW);
S6410_SetPin(Xm0CSn2_CON,LOW);
S6410_SetPin(Xm0INTsm1_FREn_CON,LOW);
S6410_SetPin(Xm0INTsm0_FWEn_CON,LOW);
S6410_SetPin(Xm0RDY1_CLE_OUT,LOW);
S6410_SetPin(Xm0RDY0_ALE_OUT,LOW);
}
static void NF_CMD(U8 cmd)
{
//Command Latch Cycle
S6410_ContRDataBus(LOW); //RD[15:0]=output
S6410_SetPin(Xm0CSn2_OUT,LOW);
S6410_SetPin(Xm0INTsm1_FREn_OUT,HIGH);
S6410_SetPin(Xm0INTsm0_FWEn_OUT,LOW); //Because tCLS=0, CLE & nFWE can be changed simultaneously.
S6410_SetPin(Xm0RDY0_ALE_OUT,LOW);
S6410_SetPin(Xm0RDY1_CLE_OUT,HIGH);
S6410_SetRDataByte(cmd);
JTAG_ShiftDRStateNoTdo(outCellValue);
S6410_SetPin(Xm0INTsm0_FWEn_OUT,HIGH);
JTAG_ShiftDRStateNoTdo(outCellValue);
#if 1
S6410_SetPin(Xm0RDY1_CLE_OUT,LOW);
//Command Latch Cycle
S6410_ContRDataBus(LOW); //RD[15:0]=output
JTAG_ShiftDRStateNoTdo(outCellValue);
#endif
}
static void NF_ADDR(U8 addr)
{
//rNFADDR=addr;
//Command Latch Cycle
S6410_ContRDataBus(LOW); //RD[15:0]=output
S6410_SetPin(Xm0CSn2_OUT,LOW);
S6410_SetPin(Xm0INTsm1_FREn_OUT,HIGH);
S6410_SetPin(Xm0INTsm0_FWEn_OUT,LOW);
S6410_SetPin(Xm0RDY0_ALE_OUT,HIGH);
S6410_SetPin(Xm0RDY1_CLE_OUT,LOW);
S6410_SetRDataByte(addr);
JTAG_ShiftDRStateNoTdo(outCellValue);
S6410_SetPin(Xm0INTsm0_FWEn_OUT,HIGH);
JTAG_ShiftDRStateNoTdo(outCellValue);
#if 1
S6410_SetPin(Xm0RDY0_ALE_OUT,LOW);
S6410_ContRDataBus(HIGH); //RD[15:0]=input
JTAG_ShiftDRStateNoTdo(outCellValue);
#endif
}
static void NF_Xm0CSn2_OUT_L(void)
{
S6410_SetPin(Xm0CSn2_CON,LOW);//Added to SJF2440
S6410_SetPin(Xm0CSn2_OUT,LOW);
JTAG_ShiftDRStateNoTdo(outCellValue);
}
static void NF_Xm0CSn2_OUT_H(void)
{
S6410_SetPin(Xm0CSn2_OUT,HIGH);
JTAG_ShiftDRStateNoTdo(outCellValue);
}
static U8 NF_RDDATA(void)
{
S6410_ContRDataBus(HIGH); //RD[15:0]=input
S6410_SetPin(Xm0INTsm1_FREn_OUT,LOW);
JTAG_ShiftDRStateNoTdo(outCellValue);
S6410_SetPin(Xm0INTsm1_FREn_OUT,HIGH);
JTAG_ShiftDRState(outCellValue,inCellValue);
return S6410_GetRDataByte();
}
static void NF_WRDATA(U8 rdata)
{
S6410_ContRDataBus(LOW); //RD[15:0]=output
S6410_SetPin(Xm0INTsm0_FWEn_OUT,LOW);
S6410_SetRDataByte(rdata);
JTAG_ShiftDRStateNoTdo(outCellValue);
S6410_SetPin(Xm0INTsm0_FWEn_OUT,HIGH);
JTAG_ShiftDRStateNoTdo(outCellValue);
}
static void NF_WAITRB(void)
{
while(1)
{
JTAG_ShiftDRState(outCellValue,inCellValue);
if( S6410_GetPin(Xm0RPn_RnB_OUT)==HIGH)
break;
}
}
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