?? ucos.lst
字號:
__text_start:
__start:
00A6 E5CF LDI R28,0x5F
00A7 E0D4 LDI R29,4
00A8 BFCD OUT 0x3D,R28
00A9 BFDE OUT 0x3E,R29
00AA 51C0 SUBI R28,0x10
00AB 40D0 SBCI R29,0
00AC EA0A LDI R16,0xAA
00AD 8308 STD Y+0,R16
00AE 2400 CLR R0
00AF E7E7 LDI R30,0x77
00B0 E0F0 LDI R31,0
00B1 E012 LDI R17,2
00B2 35E2 CPI R30,0x52
00B3 07F1 CPC R31,R17
00B4 F011 BEQ 0x00B7
00B5 9201 ST R0,Z+
00B6 CFFB RJMP 0x00B2
00B7 8300 STD Z+0,R16
00B8 E3E4 LDI R30,0x34
00B9 E0F1 LDI R31,1
00BA E6A0 LDI R26,0x60
00BB E0B0 LDI R27,0
00BC E011 LDI R17,1
00BD 34EB CPI R30,0x4B
00BE 07F1 CPC R31,R17
00BF F021 BEQ 0x00C4
00C0 95C8 LPM
00C1 9631 ADIW R30,1
00C2 920D ST R0,X+
00C3 CFF9 RJMP 0x00BD
00C4 D019 RCALL _main
_exit:
00C5 CFFF RJMP _exit
FILE: F:\ICC\project\ucos_m8_icc\test\test2.c
(0001)
(0002) #define Test1_GLOBALS
(0003) #include "includes.h"
(0004)
(0005) //******************************************************************************
(0006) // Constants
(0007) #define TaskStartPrio 10 // Task-Prioritaeten
(0008) //*****************************************************************************
(0009) // Variablen
(0010) INT8U display[5];
(0011) INT8U h,m,s,state;
(0012) OS_STK Task1Stack[OS_TASK_DEF_STK_SIZE]; // startup task stack
(0013) OS_STK Task2Stack[OS_TASK_DEF_STK_SIZE];
(0014) //ICC-AVR application builder : 2003-12-28 21:52:56
(0015) // Target : M8
(0016) // Crystal: 8.0000Mhz
(0017)
(0018) #include <iom8v.h>
(0019) #include <macros.h>
(0020) #include <stdio.h>
(0021)
(0022)
(0023) //UART0 initialisation
(0024) // desired baud rate: 9600
(0025) // actual: baud rate:9615 (0.2%)
(0026) // char size: 8 bit
(0027) // parity: Disabled
(0028) void uart0_init(void)
(0029) {
(0030) UCSRB = 0x00; //disable while setting baud rate
_uart0_init:
00C6 2422 CLR R2
00C7 B82A OUT 0x0A,R2
(0031) UCSRA = 0x00;
00C8 B82B OUT 0x0B,R2
(0032) UCSRC = 0x86;
00C9 E886 LDI R24,0x86
00CA BD80 OUT 0x20,R24
(0033) UBRRL = 0x33; //set baud rate lo
00CB E383 LDI R24,0x33
00CC B989 OUT 0x09,R24
(0034) UBRRH = 0x00; //set baud rate hi
00CD BC20 OUT 0x20,R2
(0035) UCSRB = 0x08;
00CE E088 LDI R24,0x8
00CF B98A OUT 0x0A,R24
(0036) }
00D0 9508 RET
(0037)
(0038) //*****************************************************************************
(0039) // Prototypes
(0040)
(0041) //*****************************************************************************
(0042) // TickISR
(0043) //*****************************************************************************
(0044) // Init Timer/Counter2 fuer Takterzeugung
(0045) void TC2_Init (void){
(0046) /* Only uses TIMER2 overflow for tick interrupt. Timer compare
(0047) * can also be used.
(0048) */
(0049) TIMSK &= ~(BIT(TOIE2)/* | BIT(OCIE2) */); //disable TC2 interrupts
_TC2_Init:
00D1 B789 IN R24,0x39
00D2 7B8F ANDI R24,0xBF
00D3 BF89 OUT 0x39,R24
(0050) TCCR2 = 0x00; // interner Takt, /1024
00D4 2422 CLR R2
00D5 BC25 OUT 0x25,R2
(0051) TCNT2 = 0; // Counter ruecksetzen, 2ms @ 8MHz
00D6 BC24 OUT 0x24,R2
(0052) TCCR2 = 0x04; // 64
00D7 E084 LDI R24,4
00D8 BD85 OUT 0x25,R24
(0053) // OCR2 = 180; // OutputCompareRegister
(0054) TIMSK |= BIT(TOIE2); // enable OVF-interrupt
00D9 B789 IN R24,0x39
00DA 6480 ORI R24,0x40
00DB BF89 OUT 0x39,R24
(0055) //TIMSK |= OCIE2; // enable COMP-interrupt
(0056)
(0057) SEI(); // enable global interrupt
00DC 9478 BSET 7
(0058) }
00DD 9508 RET
_main:
00DE 9723 SBIW R28,3
(0059)
(0060) //*****************************************************************************
(0061) // Interrupt Timer/Counter0 Overflow
(0062) // OVF_Takt: 4MHz / 1024 / 39 = 10ms
(0063) #pragma interrupt_handler OSTickISR:5
(0064)
(0065) void Task1(void *pdata);
(0066) void Task2(void *pdata);
(0067)
(0068) //*****************************************************************************
(0069) // Start
(0070) void main(void){
(0071) OSInit(); // OS init
00DF D120 RCALL _OSInit
(0072) uart0_init();
00E0 DFE5 RCALL _uart0_init
(0073) puts("ATmega8 uc/os-II Test!");
00E1 E600 LDI R16,0x60
00E2 E010 LDI R17,0
00E3 D767 RCALL _puts
(0074) putchar(0x0d);
00E4 E00D LDI R16,0xD
00E5 D739 RCALL _putchar
(0075) putchar(0x0a);
00E6 E00A LDI R16,0xA
00E7 D737 RCALL _putchar
(0076)
(0077) OSTaskCreate(Task1, (void *)0, &Task1Stack[OS_TASK_DEF_STK_SIZE-1], 7);
00E8 E087 LDI R24,7
00E9 838A STD Y+2,R24
00EA E38E LDI R24,0x3E
00EB E091 LDI R25,1
00EC 8399 STD Y+1,R25
00ED 8388 STD Y+0,R24
00EE 2722 CLR R18
00EF 2733 CLR R19
00F0 E208 LDI R16,0x28
00F1 E010 LDI R17,0
00F2 D4FF RCALL _OSTaskCreate
(0078)
(0079) OSTaskCreate(Task2, (void *)0, &Task2Stack[OS_TASK_DEF_STK_SIZE-1], 8);
00F3 E088 LDI R24,0x8
00F4 838A STD Y+2,R24
00F5 ED8A LDI R24,0xDA
00F6 E090 LDI R25,0
00F7 8399 STD Y+1,R25
00F8 8388 STD Y+0,R24
00F9 2722 CLR R18
00FA 2733 CLR R19
00FB E206 LDI R16,0x26
00FC E010 LDI R17,0
00FD D4F4 RCALL _OSTaskCreate
(0080) // init und start tick
(0081) TC2_Init(); // Timer/Counter#2 Overflow and Comp init
00FE DFD2 RCALL _TC2_Init
(0082) OSStart(); // start multitasking
00FF D299 RCALL _OSStart
(0083) }
0100 9623 ADIW R28,3
0101 9508 RET
_Task1:
key2 --> R12
i --> R14
key1 --> Y+0
data --> R10
0102 D719 RCALL push_gset5x
0103 0158 MOVW R10,R16
0104 9721 SBIW R28,1
(0084)
(0085) //*****************************************************************************
(0086) void Task1(void *data){
(0087) unsigned char i,key1,key2;
(0088) data = data;
(0089) PORTD |= 0x1C; // key
0105 B382 IN R24,0x12
0106 618C ORI R24,0x1C
0107 BB82 OUT 0x12,R24
(0090) DDRD &= ~0x1C;
0108 B381 IN R24,0x11
0109 7E83 ANDI R24,0xE3
010A BB81 OUT 0x11,R24
(0091) PORTD |= 0x20; // bell
010B 9A95 SBI 0x12,5
(0092) DDRD |= 0x20;
010C 9A8D SBI 0x11,5
(0093) init164(); // 顯示 初始化
010D D59C RCALL _init164
(0094) state = 1;
010E E081 LDI R24,1
010F 9380013F STS _state,R24
(0095) for (;;){
(0096) // key
(0097) key1 = PIND & 0x1C;
0111 B380 IN R24,0x10
0112 718C ANDI R24,0x1C
0113 8388 STD Y+0,R24
(0098) if(key1 == 0x1C){
0114 318C CPI R24,0x1C
0115 F559 BNE 0x0141
(0099) PORTD &= ~0x20;
0116 9895 CBI 0x12,5
(0100) if(key2 == 0x0C){
0117 2D8C MOV R24,R12
0118 308C CPI R24,0xC
0119 F431 BNE 0x0120
(0101) state ^= 0x01;
011A E081 LDI R24,1
011B 9020013F LDS R2,_state
011D 2628 EOR R2,R24
011E 9220013F STS _state,R2
(0102) }
(0103) if(state == 0){
0120 9020013F LDS R2,_state
0122 2022 TST R2
0123 F4F1 BNE 0x0142
(0104) if(key2 == 0x18){
0124 2D8C MOV R24,R12
0125 3188 CPI R24,0x18
0126 F459 BNE 0x0132
(0105) if(++s == 60) s = 0;
0127 91800140 LDS R24,_s
0129 5F8F SUBI R24,0xFF
012A 2E28 MOV R2,R24
012B 92200140 STS _s,R2
012D 338C CPI R24,0x3C
012E F419 BNE 0x0132
012F 2422 CLR R2
0130 92200140 STS _s,R2
(0106) }
(0107) if(key2 == 0x14){
0132 2D8C MOV R24,R12
0133 3184 CPI R24,0x14
0134 F469 BNE 0x0142
(0108) if(++m == 60) m = 0;
0135 91800141 LDS R24,_m
0137 5F8F SUBI R24,0xFF
0138 2E28 MOV R2,R24
0139 92200141 STS _m,R2
013B 338C CPI R24,0x3C
013C F429 BNE 0x0142
013D 2422 CLR R2
013E 92200141 STS _m,R2
(0109) }
(0110) }
(0111) }
0140 C001 RJMP 0x0142
(0112) else{
(0113) PORTD |= 0x20;
0141 9A95 SBI 0x12,5
(0114) }
(0115) key2 = key1;
0142 80C8 LDD R12,Y+0
(0116) // end key
(0117)
(0118) // display
(0119) display[0] = s%10;
0143 E01A LDI R17,0xA
0144 91000140 LDS R16,_s
0146 D697 RCALL mod8u
0147 93000143 STS _display,R16
(0120) display[1] = s/10;
0149 E01A LDI R17,0xA
014A 91000140 LDS R16,_s
014C D693 RCALL div8u
014D 93000144 STS _display+1,R16
(0121) display[2] = m%10;
014F E01A LDI R17,0xA
0150 91000141 LDS R16,_m
0152 D68B RCALL mod8u
0153 93000145 STS _display+2,R16
(0122) display[3] = m/10;
0155 E01A LDI R17,0xA
0156 91000141 LDS R16,_m
0158 D687 RCALL div8u
0159 93000146 STS _display+3,R16
(0123) switch(i){
015B 2CAE MOV R10,R14
015C 24BB CLR R11
015D 20AA TST R10
015E F411 BNE 0x0161
015F 20BB TST R11
0160 F071 BEQ 0x016F
0161 01C5 MOVW R24,R10
0162 3081 CPI R24,1
0163 E0E0 LDI R30,0
0164 079E CPC R25,R30
0165 F099 BEQ 0x0179
0166 3082 CPI R24,2
0167 E0E0 LDI R30,0
0168 079E CPC R25,R30
0169 F0C9 BEQ 0x0183
016A 3083 CPI R24,3
016B E0E0 LDI R30,0
016C 079E CPC R25,R30
016D F0F9 BEQ 0x018D
016E C027 RJMP 0x0196
(0124) case 0: write164(display[i] | 0x70); break;
016F E483 LDI R24,0x43
0170 E091 LDI R25,1
0171 2DEE MOV R30,R14
0172 27FF CLR R31
0173 0FE8 ADD R30,R24
0174 1FF9 ADC R31,R25
0175 8100 LDD R16,Z+0
0176 6700 ORI R16,0x70
0177 D537 RCALL _write164
0178 C01D RJMP 0x0196
(0125) case 1: write164(display[i] | 0xB0); break;
0179 E483 LDI R24,0x43
017A E091 LDI R25,1
017B 2DEE MOV R30,R14
017C 27FF CLR R31
017D 0FE8 ADD R30,R24
017E 1FF9 ADC R31,R25
017F 8100 LDD R16,Z+0
0180 6B00 ORI R16,0xB0
0181 D52D RCALL _write164
0182 C013 RJMP 0x0196
(0126) case 2: write164(display[i] | 0xD0); break;
0183 E483 LDI R24,0x43
0184 E091 LDI R25,1
0185 2DEE MOV R30,R14
0186 27FF CLR R31
0187 0FE8 ADD R30,R24
0188 1FF9 ADC R31,R25
0189 8100 LDD R16,Z+0
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