Timing Analyzer report for ad
Tue Apr 21 15:31:29 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                              ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From     ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 9.090 ns                         ; clk_10   ; sck      ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 164.02 MHz ( period = 6.097 ns ) ; count[7] ; count[0] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;          ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM570GT144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                       ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From     ; To       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 164.02 MHz ( period = 6.097 ns )               ; count[7] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 5.388 ns                ;
; N/A   ; 164.04 MHz ( period = 6.096 ns )               ; count[7] ; count[6] ; clk        ; clk      ; None                        ; None                      ; 5.387 ns                ;
; N/A   ; 166.81 MHz ( period = 5.995 ns )               ; count[1] ; count[7] ; clk        ; clk      ; None                        ; None                      ; 5.286 ns                ;
; N/A   ; 167.00 MHz ( period = 5.988 ns )               ; count[1] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 5.279 ns                ;
; N/A   ; 167.11 MHz ( period = 5.984 ns )               ; count[1] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 5.275 ns                ;
; N/A   ; 170.82 MHz ( period = 5.854 ns )               ; count[2] ; count[7] ; clk        ; clk      ; None                        ; None                      ; 5.145 ns                ;
; N/A   ; 171.03 MHz ( period = 5.847 ns )               ; count[2] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 5.138 ns                ;
; N/A   ; 171.14 MHz ( period = 5.843 ns )               ; count[2] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 5.134 ns                ;
; N/A   ; 171.73 MHz ( period = 5.823 ns )               ; count[1] ; count[6] ; clk        ; clk      ; None                        ; None                      ; 5.114 ns                ;
; N/A   ; 172.89 MHz ( period = 5.784 ns )               ; count[1] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 5.075 ns                ;
; N/A   ; 173.16 MHz ( period = 5.775 ns )               ; count[0] ; count[6] ; clk        ; clk      ; None                        ; None                      ; 5.066 ns                ;
; N/A   ; 174.00 MHz ( period = 5.747 ns )               ; count[3] ; count[7] ; clk        ; clk      ; None                        ; None                      ; 5.038 ns                ;
; N/A   ; 174.22 MHz ( period = 5.740 ns )               ; count[3] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 5.031 ns                ;
; N/A   ; 174.34 MHz ( period = 5.736 ns )               ; count[3] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 5.027 ns                ;
; N/A   ; 175.22 MHz ( period = 5.707 ns )               ; count[4] ; count[7] ; clk        ; clk      ; None                        ; None                      ; 4.998 ns                ;
; N/A   ; 175.56 MHz ( period = 5.696 ns )               ; count[4] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 4.987 ns                ;
; N/A   ; 175.81 MHz ( period = 5.688 ns )               ; count[0] ; count[7] ; clk        ; clk      ; None                        ; None                      ; 4.979 ns                ;
; N/A   ; 175.99 MHz ( period = 5.682 ns )               ; count[2] ; count[6] ; clk        ; clk      ; None                        ; None                      ; 4.973 ns                ;
; N/A   ; 176.03 MHz ( period = 5.681 ns )               ; count[0] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 4.972 ns                ;