# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c6SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Multiplier family Xilinx,_Inc. 8.0# END Select# BEGIN ParametersCSET pipelined=MaximumCSET output_width=24CSET asynchronous_clear=falseCSET synchronous_clear=falseCSET memory_type=Distributed_MemoryCSET clock_enable=falseCSET port_a_data=SignedCSET load_done_output=falseCSET ce_overrides=SCLR_Overrides_CECSET nd=falseCSET register_input=falseCSET port_b_width=12CSET port_b_data=SignedCSET port_b_constant_value=10CSET port_a_width=12CSET component_name=multCSET multiplier_construction=Use_LUTsCSET output_options=RegisteredCSET port_b_constant=falseCSET reload_options=Stop_During_ReloadCSET rfd=falseCSET reloadable=falseCSET rdy=false# END ParametersGENERATE