Assembler report for CCD
Tue Apr 21 15:05:50 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
  5. Assembler Device Options: E:/FPGA practice/CCD/CCD.pof
  6. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Tue Apr 21 15:05:50 2009 ;
; Revision Name         ; CCD                                   ;
; Top-level Entity Name ; CCD                                   ;
; Family                ; MAX7000S                              ;
; Device                ; EPM7064SLC84-6                        ;
+-----------------------+---------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                     ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option                                                                      ; Setting  ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation                                                       ; Off      ; Off           ;
; Compression mode                                                            ; Off      ; Off           ;
; Clock source for configuration device                                       ; Internal ; Internal      ;
; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
; Divide clock frequency by                                                   ; 1        ; 1             ;
; Auto user code                                                              ; Off      ; Off           ;
; Security bit                                                                ; Off      ; Off           ;
; Use configuration device                                                    ; On       ; On            ;
; Configuration device auto user code                                         ; Off      ; Off           ;
; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
; Hexadecimal Output File start address                                       ; 0        ; 0             ;
; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
+-----------------------------------------------------------------------------+----------+---------------+


+------------------------------+
; Assembler Generated Files    ;
+------------------------------+
; File Name                    ;
+------------------------------+
; E:/FPGA practice/CCD/CCD.pof ;
+------------------------------+


+--------------------------------------------------------+
; Assembler Device Options: E:/FPGA practice/CCD/CCD.pof ;
+----------------+---------------------------------------+
; Option         ; Setting                               ;
+----------------+---------------------------------------+
; Device         ; EPM7064SLC84-6                        ;
; JTAG usercode  ; 0x00000000                            ;
; Checksum       ; 0x000D6274                            ;
+----------------+---------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Tue Apr 21 15:05:49 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CCD -c CCD
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Tue Apr 21 15:05:51 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01