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# Reading D:/tools/modelsim6/tcl/vsim/pref.tcl
# // ModelSim SE 6.0 Aug 19 2004
# //
# // Copyright Mentor Graphics Corporation 2004
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do led1.tdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity led
# -- Compiling architecture structure of led
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity led1
# -- Compiling architecture testbench_arch of led1
# vsim -lib work -sdfmax /UUT=led_timesim.sdf -t 1ps led1
# Loading D:\tools\modelsim6\win32/../std.standard
# Loading D:\tools\modelsim6\win32/../ieee.std_logic_1164(body)
# Loading D:\tools\modelsim6\win32/../ieee.std_logic_arith(body)
# Loading D:\tools\modelsim6\win32/../ieee.std_logic_unsigned(body)
# Loading D:\tools\modelsim6\win32/../std.textio(body)
# Loading D:\tools\modelsim6\win32/../ieee.std_logic_textio(body)
# Loading work.led1(testbench_arch)
# Loading D:\tools\modelsim6\win32/../vital2000.vital_timing(body)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.vcomponents
# Loading D:\tools\modelsim6\win32/../vital2000.vital_primitives(body)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.vpackage(body)
# Loading work.led(structure)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.x_buf(x_buf_v)
# Loading led_timesim.sdf
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.x_xor2(x_xor2_v)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.x_zero(x_zero_v)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.x_and2(x_and2_v)
# Loading D:/tools/ISE7.1/vhdl/mti_se/simprim.x_one(x_one_v)
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /led1 File: led1.timesim_vhw
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Error: Error at time=115ns led1=0, Expected = 1
# Time: 115 ns Iteration: 0 Instance: /led1
# ** Failure: Errors found during simulation
# Time: 1200 ns Iteration: 0 Process: /led1/line__73 File: led1.timesim_vhw
# Break at led1.timesim_vhw line 152
# Simulation Breakpoint: Break at led1.timesim_vhw line 152
# MACRO ./led1.tdo PAUSED at line 14
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