?? cstartup.s79
字號:
;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbols ?cstartup etc.
; If this entire file is assembled and linked with the provided
; libraries, the XLINK option -C must be used to avoid a clash with
; PROGRAM module ?RESET.
; EWARM also has a check box to "Ignore CSTARTUP in library", that has
; the same effect.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment,
; that must be reachable by a B instruction in ARM mode from segment INTVEC
; (within the first 32 Mbytes).
;
; Define preprocessor symbol __THUMB_LIBRARY__ for Thumb libraries
; or __ARM_LIBRARIES__ for ARM libraries.
;
; $Revision: 1.29 $
;
;-----------------------------------------------------------------------------
#include "compiler_option.h"
#include "4510addr.a"
#include "memcfg.a"
; Make sure that __ARM_LIBRARY__ or __THUMB_LIBRARY__ is defined
#ifdef __ARM_LIBRARY__
#ifdef __THUMB_LIBRARY__
#error "Cannot have both __ARM_LIBRARY__ and __THUMB_LIBRARY__ set!"
#endif
#else
#ifndef __THUMB_LIBRARY__
#error "Must have one of __ARM_LIBRARY__ or __THUMB_LIBRARY__ set!"
#endif
#endif
;
; Naming covention of labels in this file:
;
; ?xxx - External labels only accessed from assembler.
; __xxx - External labels accessed from or defined in C.
; xxx - Labels local to one module (note: this file contains
; several modules).
; main - The starting point of the user program.
;
;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
USER_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABORT_MODE DEFINE 0x17 ; Abort mode
UNDEF_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode
MODE_MASK DEFINE 0x1f
NOINT DEFINE 0xc0
ROM0_SIZE DEFINE 0x200000
SDRAM0_BASE_FOR_LOADER DEFINE 0x1000000
#if __LITTLE_ENDIAN__==1
; RTMODEL attribute __endian
#define ENDIAN_MODE "little"
#else
#define ENDIAN_MODE "big"
#endif
#ifdef __THUMB_LIBRARY__
; RTMODEL attribute __cpu_mode
#define CPU_MODE_NAME "thumb"
; Segment used for libraries
#define LIB_SEGMENT NEARFUNC_T
SEGMENT_ALIGN DEFINE 1 ; Align Thumb segments to 2^1
CPU_MODE MACRO
CODE16
ENDM
#else /////// __ARM_LIBRARY__
; RTMODEL attribute __cpu_mode
#define CPU_MODE_NAME "arm"
; Segment used for libraries
#define LIB_SEGMENT NEARFUNC_A
SEGMENT_ALIGN DEFINE 2 ; Align ARM segments to 2^2
CPU_MODE MACRO
CODE32
ENDM
#endif
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------
PROGRAM ?RESET
COMMON INTVEC:CODE:ROOT(2)
EXTERN Addr_Reset,Addr_Undefined,Addr_Swi,Addr_Prefetch,Addr_Prefetch,Addr_Dabort,Addr_IRQ,Addr_FIQ
CODE32 ; Always ARM mode after reset
org 0
reset
LDR PC, Addr_Reset
LDR PC, Addr_Undefined
LDR PC, Addr_Swi
LDR PC, Addr_Prefetch
LDR PC, Addr_Dabort
b . ; Reserved
LDR PC, Addr_IRQ
LDR PC, Addr_FIQ
ENDMOD
;---------------------------------------------------------------
; ?BOOT
;---------------------------------------------------------------
HANDLER MACRO HandlerLabel, HandleLabel
HandlerLabel:
SUB sp,sp,#4 ;decrement sp(to store jump address)
STMFD sp!,{r0} ;PUSH the work register to stack(lr does't push because it return to original address)
LDR r0,=HandleLabel;load the address of HandleXXX to r0
LDR r0,[r0] ;load the contents(service routine start address) of HandleXXX
STR r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
LDMFD sp!,{r0,pc} ;POP the work register and pc(jump to ISR)
ENDM
PROGRAM ?BOOT
RSEG ICODE:CODE:NOROOT(2)
EXTERN ?cstartup
CODE32
PUBLIC Addr_Reset,Addr_Undefined,Addr_Swi,Addr_Prefetch,Addr_Prefetch,Addr_Dabort,Addr_IRQ,Addr_FIQ
EXTERN pISR_Reset, pISR_Undef, pISR_SWI, pISR_Pabort, pISR_Dabort
EXTERN pISR_Reserved, pISR_IRQ, pISR_FIQ
EXTERN pISR_EXT0
ResetHandler
?boot:
LDR r0,=INTMSK
LDR r1,=0x003FFFFF ;all interrupt disable
STR r1,[r0]
;
;Set memory control registers
;
LDR r0,=SMRDATA
LDR r1,=SYSCON ;SYSCON Address
LDR r3, [r0], #4
STR r3, [r1], #0
LDR r1,=CLKCON ;CLKCON Address
LDR r3, [r0], #4
STR r3, [r1], #0
LDR R0,=SMRDATA1
LDMIA R0,{R1-R3}
LDR R0,=EXTACON0
STMIA R0,{R1-R3}
#ifdef LOADER
LDR R0,=LOADER_MAP
LDMIA R0,{R1-R11}
LDR R0,=ROMCON0
STMIA R0,{R1-R11}
LDR R0,=0
LDR R1,=ROM0_SIZE
LDR R2,=SDRAM0_BASE_FOR_LOADER
Relocate:
LDR R3,[R0],#4
STR R3,[R2],#4
SUBS R1,R1,#4
BNE Relocate
#endif
LDR R0,=SMRDATA2
LDMIA R0,{R1-R11}
LDR R0,=ROMCON0
STMIA R0,{R1-R11}
; Setup IRQ handler
LDR r0,=pISR_IRQ ;This routine is needed
LDR r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
STR r1,[r0]
; ########## Initial critical IO
; ...
; ########## Execute C startup code.
b ?cstartup
IsrIRQ
SUB sp,sp,#4 ;reserved for PC
STMFD sp!,{r8-r9}
LDR r9,=INTOSET_IRQ
LDR r9,[r9]
LDR r8,=pISR_EXT0
LDR r8,[r8,r9]
STR r8,[sp,#8]
LDMFD sp!,{r8-r9,pc}
; Put constant table here.
LTORG
SMRDATA:
DC32 ((SYS_SDM<<31)+(SYS_PD_ID<<26)+(SYS_SFR_SADDR<<16)+(SYS_SRAM_SADDR<<6)+(SYS_CM<<4)+(SYS_WE<<2)+(SYS_CE<<1)+(SYS_SE)) ; SYSCON
DC32 ((CLK_TAC<<18)+(CLK_R5MUX<<17)+(CLK_R5WAIT<<16)+(CLK_DIVIDING)) ; CLKCON
SMRDATA1
DC32 ((IO1_TACC<<25)+(IO1_TCOH<<22)+(IO1_TACS<<19)+(IO1_TCOS<<16)+(IO0_TACC<<9)+(IO0_TCOH<<6)+(IO0_TACS<<3)+(IO0_TCOS)) ; EXTACON0
DC32 ((IO3_TACC<<25)+(IO3_TCOH<<22)+(IO3_TACS<<19)+(IO3_TCOS<<16)+(IO1_TACC<<9)+(IO1_TCOH<<6)+(IO1_TACS<<3)+(IO1_TCOS)) ; EXTACON1
DC32 ((IO3_BWSCON<<26)+(IO2_BWSCON<<24)+(IO1_BWSCON<<22)+(IO0_BWSCON<<20)+(DR3_BWSCON<<18)+(DR2_BWSCON<<16)+(DR1_BWSCON<<14)+(DR0_BWSCON<<12)+(R5_BWSCON<<10)+(R4_BWSCON<<8)+(R3_BWSCON<<6)+(R2_BWSCON<<4)+(R1_BWSCON<<2)+(R0_BWSCON)) ; EXTDBWTH
SMRDATA2
DC32 ((R0_NSADDR<<20)+(R0_SADDR<<10)+(R0_TACC<<4)+(R0_TPA<<2)+R0_PMC) ; ROMCON0
DC32 ((R1_NSADDR<<20)+(R1_SADDR<<10)+(R1_TACC<<4)+(R1_TPA<<2)+R1_PMC) ; ROMCON0
DC32 ((R2_NSADDR<<20)+(R2_SADDR<<10)+(R2_TACC<<4)+(R2_TPA<<2)+R2_PMC) ; ROMCON0
DC32 ((R3_NSADDR<<20)+(R3_SADDR<<10)+(R3_TACC<<4)+(R3_TPA<<2)+R3_PMC) ; ROMCON0
DC32 ((R4_NSADDR<<20)+(R4_SADDR<<10)+(R4_TACC<<4)+(R4_TPA<<2)+R4_PMC) ; ROMCON0
DC32 ((R5_NSADDR<<20)+(R5_SADDR<<10)+(R5_TACC<<4)+(R5_TPA<<2)+R5_PMC) ; ROMCON0
DC32 ((DR0_NSADDR<<20)+(DR0_SADDR<<10)+(DR0_TRP<<8)+(DR0_TRC<<7)+(DR0_TCP<<3)+(DR0_TCS<<1)+DR0_EDO)
DC32 ((DR1_NSADDR<<20)+(DR1_SADDR<<10)+(DR1_TRP<<8)+(DR1_TRC<<7)+(DR0_TCP<<3)+(DR1_TCS<<1)+DR1_EDO)
DC32 ((DR2_NSADDR<<20)+(DR2_SADDR<<10)+(DR2_TRP<<8)+(DR2_TRC<<7)+(DR0_TCP<<3)+(DR2_TCS<<1)+DR2_EDO)
DC32 ((DR3_NSADDR<<20)+(DR3_SADDR<<10)+(DR3_TRP<<8)+(DR3_TRC<<7)+(DR0_TCP<<3)+(DR3_TCS<<1)+DR3_EDO)
DC32 ((REF_CNT<<21)+(REF_TCSR<<20)+(REF_TCHR<<17)+(REF_REN<<16)+(REF_VSF<<15)+REF_SADDR) ; REFEXTCON
#ifdef LOADER
LOADER_MAP
DC32 ((0x1f<<20)+(0<<10)+(R0_TACC<<4)+(R0_TPA<<2)+R0_PMC) ; ROMCON0
DC32 ((R1_NSADDR<<20)+(R1_SADDR<<10)+(R1_TACC<<4)+(R1_TPA<<2)+R1_PMC) ; ROMCON0
DC32 ((R2_NSADDR<<20)+(R2_SADDR<<10)+(R2_TACC<<4)+(R2_TPA<<2)+R2_PMC) ; ROMCON0
DC32 ((R3_NSADDR<<20)+(R3_SADDR<<10)+(R3_TACC<<4)+(R3_TPA<<2)+R3_PMC) ; ROMCON0
DC32 ((R4_NSADDR<<20)+(R4_SADDR<<10)+(R4_TACC<<4)+(R4_TPA<<2)+R4_PMC) ; ROMCON0
DC32 ((R5_NSADDR<<20)+(R5_SADDR<<10)+(R5_TACC<<4)+(R5_TPA<<2)+R5_PMC) ; ROMCON0
DC32 ((0x2ff<<20)+(0x100<<10)+(DR0_TRP<<8)+(DR0_TRC<<7)+(DR0_TCP<<3)+(DR0_TCS<<1)+DR0_EDO)
DC32 ((DR1_NSADDR<<20)+(DR1_SADDR<<10)+(DR1_TRP<<8)+(DR1_TRC<<7)+(DR0_TCP<<3)+(DR1_TCS<<1)+DR1_EDO)
DC32 ((DR2_NSADDR<<20)+(DR2_SADDR<<10)+(DR2_TRP<<8)+(DR2_TRC<<7)+(DR0_TCP<<3)+(DR2_TCS<<1)+DR2_EDO)
DC32 ((DR3_NSADDR<<20)+(DR3_SADDR<<10)+(DR3_TRP<<8)+(DR3_TRC<<7)+(DR0_TCP<<3)+(DR3_TCS<<1)+DR3_EDO)
DC32 ((REF_CNT<<21)+(REF_TCSR<<20)+(REF_TCHR<<17)+(REF_REN<<16)+(REF_VSF<<15)+REF_SADDR) ; REFEXTCON
#endif
SMRDATA_END
Addr_Reset DC32 ResetHandler
Addr_Undefined DC32 HandlerUndef
Addr_Swi DC32 HandlerSWI
Addr_Prefetch DC32 HandlerPabort
Addr_Dabort DC32 HandlerDabort
DC32 0 ; Reserved
Addr_IRQ DC32 HandlerIRQ
Addr_FIQ DC32 HandlerFIQ
; ************************
; Exception Handlers
; ************************
LTORG
HANDLER HandlerFIQ, pISR_FIQ
HANDLER HandlerIRQ,pISR_IRQ
HANDLER HandlerUndef,pISR_Undef
HANDLER HandlerSWI,pISR_SWI
HANDLER HandlerDabort,pISR_Dabort
HANDLER HandlerPabort,pISR_Pabort
ENDMOD ?boot ; Entry point = ?boot
;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
PROGRAM ?CSTARTUP
; RTMODEL attributes ensure that
; RTMODEL "__rt_version", "4"
RTMODEL "__endian", ENDIAN_MODE
RTMODEL "__thumb_aware", "enabled"
; RTMODEL "__cpu_mode", "*" ; CPU_MODE_NAME
; RTMODEL "__code_model", "*" ; Match all code models
; Declare segment used with SFE below
#ifdef _ECPLUSPLUS
RSEG DIFUNCT(2)
#endif /* _ECPLUSPLUS */
RSEG IRQ_STACK:DATA(2)
RSEG FIQ_STACK:DATA(2)
RSEG SVC_STACK:DATA:NOROOT(2)
RSEG CSTACK:DATA(2)
RSEG ICODE:CODE:NOROOT(2)
PUBLIC ?cstartup
EXTERN __segment_init
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