; =====================================================================================
; SYSCFG Register
;[0] Stall enable (SE)
;	Must be set to zero.
;[1] Cache enable (CE)
;	When set to ¨1〃, cache operations are enabled.
;[2] Write buffer enable (WE)
;	When set to ¨1〃, write buffer operations are;enabled.
;[5:4] Cache mode (CM)
;	This 2-bit value determines how internal memory is
;	to be divided into cache and SRAM.
;	00 = 4-Kbyte SRAM, 4-Kbyte cache
;	01 = 0-Kbyte SRAM, 8-Kbyte cache
;	10 = 8-Kbyte SRAM, 0-Kbyte cache
;	NOTE: When you write 10 to this field, the cache
;	enable bit is cleared automatically.
;[15:6] Internal SRAM base pointer
;	This 10-bit address becomes the upper address
;	of SRAM. A25 through A16, the remaining SRAM
;	addresses, and A15 through A0, are filled with zeros.
;[25:16] Special register bank base pointer
;	The resolution of this value is 64 K. Therefore, to
;	place the start address at 1800000H (24 M), use this
;	formula:
;	Setting value = (1800000H / 64 K) << 16.
;[29:26] Product Identifier (PD_ID)
;	0000 = KS32C5000
;	0001 = KS32C50100
;[31] Sync. DRAM Mode
;	0 = Normal/EDO DRAM interface for 4 DRAM banks
;	1 = Sync. DRAM interface for 4 DRAM banks
; =====================================================================================
CACHE_DISABLE	DEFINE	0
CACHE_ENABLE	DEFINE	1
SYS_SE		DEFINE	0
SYS_CE		DEFINE	CACHE_DISABLE
SYS_WE		DEFINE	0
SYS_CM		DEFINE	1	; 0-Kbyte SRAM, 8-Kbyte cache
SYS_SRAM_SADDR	DEFINE	0x3FE	; Internal SRAM Start Address = 0x3FE0000
SYS_SFR_SADDR	DEFINE	0x3FF	; SFR Start Address = 0x3FF0000
SYS_PD_ID	DEFINE	1	; KS32C50100
SYS_SDM		DEFINE	1	; 1 = Sync. DRAM interface for 4 DRAM banks




; =====================================================================================
; CLKCON
;
;[15:0] Clock dividing value
;	If all bits are 0, a non-divided clock is used. Only one bit
;	can be set in CLKCON[15:0]. That is, the clock dividing
;	value is defined as 1, 2, 4, 8,16, ....
;	Internal system clock, f MCLK = f ICLK / (CLKCON+1)
;[16] ROM bank 5 wait enable
;	0 = Disable ROM bank 5 wait.
;	1 = Enable ROM bank 5 wait.
;[17] ROM bank 5 address/data bus Mux enable
;	0 = Normal operation
;	1 = Enable bus multiplexing
;[19:18] Mux bus Address Cycle (tAC)
;	00 = 1 MCLK
;	01 = 2 MCLK
;	10 = 3 MCLK
;[31] Test bit
;	This bit should be always 0.
; =====================================================================================
CLK_DIVIDING	DEFINE	0
CLK_R5WAIT	DEFINE	0	; Disable
CLK_R5MUX	DEFINE	0	; Normal operation
CLK_TAC		DEFINE	0	; 1 MCLK

; =====================================================================================
;EXTDBWTH
;[1:0] 	Data bus width for ROM/SRAM/FLASH bank 0 (DSR0)
;	DSR0 is read-only data at the B0SIZE [1:0] pins. DSR0 is read-only because
;	ROM/SRAM/FLASH bank 0 is used to boot the ROM while the data bus width
;	for ROM/SRAM/FLASH bank 0 is set using B0SIZE [1:0].
;	00 = Not permitted
;	01 = Byte (8 bits)
;	10 = Half-word (16 bits)
;	11 = Word (32 bits)
;[3:2] Data bus width for ROM/SRAM/FLASH bank 1 (DSR1)
;[5:4] DSR2, [7:6] DSR3, [9:8] DSR4, [11:10] DSR5
;	00 = Disable
;	01 = Byte (8 bits)
;	10 = Half-word (16 bits)
;	11 = Word (32 bits)
;[13:12] Data bus width for DRAM bank 0 (DSD0)
;[15:14] DSD1, [17:16] DSD2, [19:18] DSD3
;	00 = Disable
;	01 = Byte (8 bits)
;	10 = Half-word (16 bits)
;	11 = Word (32 bits)
;[21:20] Data bus width for external I/O bank 0 (DSX0)
;[23:22] DSX1, [25:24] DSX2, [27:26] DSX3
;	00 = Disable
;	01 = Byte (8 bits)
;	10 = Half-word (16 bits)
;	11 = Word (32 bits)
; =====================================================================================
BUS_DISABLE	DEFINE	(00)
DW8			DEFINE	(0x1)
DW16		DEFINE	(0x2)
DW32		DEFINE	(0x3)

R0_BWSCON	DEFINE (DW16)
R1_BWSCON	DEFINE (BUS_DISABLE)
R2_BWSCON	DEFINE (BUS_DISABLE)
R3_BWSCON	DEFINE (BUS_DISABLE)
R4_BWSCON	DEFINE (DW32)
R5_BWSCON	DEFINE (DW32)

DR0_BWSCON	DEFINE (DW32)
DR1_BWSCON	DEFINE (BUS_DISABLE)
DR2_BWSCON	DEFINE (BUS_DISABLE)
DR3_BWSCON	DEFINE (BUS_DISABLE)

IO0_BWSCON	DEFINE (DW16)
IO1_BWSCON	DEFINE (DW16)
IO2_BWSCON	DEFINE (DW16)
IO3_BWSCON	DEFINE (DW16)


; =====================================================================================
; External I/O access timing register 0/1
;[2:0] Chip selection set-up time on nOE (tCOS0, tCOS2)
;[18:16] tCOS1, tCOS3
;	000 = 0 cycle 100 = 4 cycles
;	001 = 1 cycles 101 = 5 cycles
;	010 = 2 cycle 110 = 6 cycles
;	011 = 3 cycles 111 = 7 cycles
;[5:3] Address set-up time before nECS (tACS0, tACS2)
;[21:19] tACS1, tACS3
;	000 = 0 cycle 100 = 4 cycles
;	001 = 1 cycles 101 = 5 cycles
;	010 = 2 cycle 110 = 6 cycles
;	011 = 3 cycles 111 = 7 cycles
;[8:6] Chip selection hold time on nOE (tCOH0, tCOH2)
;[24:22] tCOH1, tCOH3
;	000 = 0 cycle 100 = 4 cycles
;	001 = 1 cycles 101 = 5 cycles
;	010 = 2 cycle 110 = 6 cycles
;	011 = 3 cycles 111 = 7 cycles
;[11:9] Access cycles (nOE Low time) (tACC0, tACC2)
;[27:25] tACC1, tACC3
;	000 = 0 cycle 100 = 4 cycles
;	001 = 1 cycles 101 = 5 cycles
;	010 = 2 cycle 110 = 6 cycles
;	011 = 3 cycles 111 = 7 cycles
; =====================================================================================
;
IO0_TCOS	DEFINE	2	; 7 Cycles
IO0_TACS	DEFINE	2	; 7 Cycles
IO0_TCOH	DEFINE	2	; 7 Cycles
IO0_TACC	DEFINE	5	; 7 Cycles
IO1_TCOS	DEFINE	7	; 7 Cycles
IO1_TACS	DEFINE	7	; 7 Cycles
IO1_TCOH	DEFINE	7	; 7 Cycles
IO1_TACC	DEFINE	7	; 7 Cycles
IO2_TCOS	DEFINE	7	; 7 Cycles
IO2_TACS	DEFINE	7	; 7 Cycles
IO2_TCOH	DEFINE	7	; 7 Cycles
IO2_TACC	DEFINE	7	; 7 Cycles
IO3_TCOS	DEFINE	7	; 7 Cycles
IO3_TACS	DEFINE	7	; 7 Cycles
IO3_TCOH	DEFINE	7	; 7 Cycles
IO3_TACC	DEFINE	7	; 7 Cycles



; =====================================================================================
;ROMCONn Bit Description
; Page Mode configuration(PMC)
;[1:0] Page mode configuration (PMC)
;00 = Normal R  01 = 4-word page
;10 = 8-word page 11 = 16-word page

;[3:2] Page address access time (tPA)
;00 = 5 cycles 01 = 2 cycles
;10 = 3 cycles 11 = 4 cycles
;

;[6:4] Programmable access cycle (tACC)
;000 = Disable bank 001 = 2 cycles
;010 = 3 cycles 011 = 4 cycles
;100 = 5 cycles 101 = 6 cycles
;110 = 7 cycles 111 = Reserved

;[19:10] R/SRAM/Flash bank # base pointer
;This value is the start address of the R/SRAM/Flash bank #.
;The start address is calculated as R/SRAM/FLASH bank # base
;pointer << 16

;[29:20] R/SRAM/FLASH bank # next pointer
;This value is the current bank end address << 16 + 1
;
; =====================================================================================

; ROMCON0 : 0x20000060 after Reset 
;

R0_PMC		DEFINE	0	; Normal R
R0_TPA		DEFINE	0	; 5 cycles
R0_TACC		DEFINE	4	; 5 cycles
R0_SADDR	DEFINE	0x180	; Start Address = 0x01800000
R0_NSADDR	DEFINE	0x1A0	; End   Address = 0x01A00000-1

; ROMCON1 : 0x00000060 after Reset 
;
R1_PMC		DEFINE	0	; Normal R
R1_TPA		DEFINE	0	; 5 cycles
R1_TACC		DEFINE	6	; 7 cycles
R1_SADDR	DEFINE	0	; Start Address = 0
R1_NSADDR	DEFINE	0    	; Next R Address;

; ROMCON2 : 0x00000060 after Reset 
;
R2_PMC		DEFINE	0	; Normal R
R2_TPA		DEFINE	0	; 5 cycles
R2_TACC		DEFINE	6	; 7 cycles
R2_SADDR	DEFINE	0	; Start Address = 0
R2_NSADDR	DEFINE	0   	; Next R Address;

; ROMCON3 : 0x00000060 after Reset 
;
R3_PMC		DEFINE	0	; Normal R
R3_TPA		DEFINE	0	; 5 cycles
R3_TACC		DEFINE	6	; 7 cycles
R3_SADDR	DEFINE	0	; Start Address = 0
R3_NSADDR	DEFINE	0    	; Next R Address;

; ROMCON4 : 0x00000060 after Reset 
;
R4_PMC		DEFINE	0	; Normal R
R4_TPA		DEFINE	0	; 5 cycles
R4_TACC		DEFINE	6	; 7 cycles
R4_SADDR	DEFINE	0	; Start Address = 0
R4_NSADDR	DEFINE	0    	; Next R Address;

; ROMCON5 : 0x00000060 after Reset 
;
R5_PMC		DEFINE	0	; Normal R
R5_TPA		DEFINE	0	; 5 cycles
R5_TACC		DEFINE	6	; 7 cycles
R5_SADDR	DEFINE	0	; Start Address = 0
R5_NSADDR	DEFINE	0    	; Next R Address;

; =====================================================================================
;DRAM Parameter 
;DRAMCON#
; =====================================================================================
;[0] EDO mode (EDO) (note)
;	0 = Normal DRAM (Fast page mode DRAM)
;	1 = EDO DRAM
;[2:1] CAS strobe time (tCS)
;	00 = 1 cycle 01 = 2 cycles
;	10 = 3 cycles 11 = 4 cycles
;[3:3] CAS pre-charge time (tCP) (note)
;	0 = 1 cycle 1 = 2 cycles
;[6:4] Reserved
;	These bits default value is 000. But, you must set to 001.
;
;[7] RAS to CAS delay (tRC or tRCD)
;	0 = 1 cycle 1 = 2 cycles
;
;[9:8] RAS pre-charge time (tRP)
;	00 = 1 cycle 01 = 2 cycles
;	10 = 3 cycles 11 = 4 cycles
;
;[19:10] DRAM bank # base pointer
;This value indicates the start address of DRAM bank #. The start address is
;calculated as RAM bank # base pointer << 16
;
;[29:20] DRAM bank # Next pointer
;This value is the current bank end address << 16 + 1
;
;[31:30] Number of column address bits in DRAM bank # (CAN)
;	00 = 8 bits 01 = 9 bits
;	10 = 10 bits 11 = 11 bits
;

; DRAMCON0 : 0x00000000 after Reset 
;
DR0_EDO		DEFINE	1	; 
DR0_TCS		DEFINE	0	;
DR0_TCP		DEFINE	0	; 
DR0_TRC		DEFINE	0	; 
DR0_TRP		DEFINE	3    	; 
DR0_SADDR	DEFINE	0	; Start Address = 0x00000000 
DR0_NSADDR	DEFINE	0x100	; End   Address = 0x01000000-1

; DRAMCON1 : 0x00000000 after Reset 
;
DR1_EDO		DEFINE	0	; 
DR1_TCS		DEFINE	0	;
DR1_TCP		DEFINE	0	; 
DR1_TRC		DEFINE	0	; 
DR1_TRP		DEFINE	0   	; 
DR1_SADDR	DEFINE	0	;
DR1_NSADDR	DEFINE	0	;

; DRAMCON2 : 0x00000000 after Reset 
;
DR2_EDO		DEFINE	0	; 
DR2_TCS		DEFINE	0	;
DR2_TCP		DEFINE	0	; 
DR2_TRC		DEFINE	0	; 
DR2_TRP		DEFINE	0    	; 
DR2_SADDR	DEFINE	0	;
DR2_NSADDR	DEFINE	0	;

; DRAMCON3 : 0x00000000 after Reset 
;
DR3_EDO		DEFINE	0	; 
DR3_TCS		DEFINE	0	;
DR3_TCP		DEFINE	0	; 
DR3_TRC		DEFINE	0	; 
DR3_TRP		DEFINE	0   	; 
DR3_SADDR	DEFINE	0	;
DR3_NSADDR	DEFINE	0	;


; =====================================================================================
; REFEXTCON
;======================================================================================
;[9:0] 	External I/O bank 0 base pointer (base address)
;	This value is the start address of external I/O bank 0. Start address is defined as
;	External I/O bank 0 base pointer << 16. The end address of external I/O bank 0 is
;	defined as External I/O bank 0 base pointer >> 16 + 16 K bytes - 1.
;	NOTE: All external I/O banks are located in the continuous address space which
;	begins at the start address of external I/O bank 0. The size of each external I/O
;	bank is fixed at 16 K bytes. The start and end addresses of the other three external
;	I/O banks can be derived from the external I/O bank 0 base pointer value.
;
;[15] 	Validity of special register field (VSF)
;	0 = Not accessible to memory bank
;	1 = Accessible to memory bank
;[16] 	Refresh enable (REN)
;	0 = Disable DRAM refresh
;	1 = Enable DRAM refresh
;[19:17] CAS hold time (tCHR)
;	ROW Cycle Time (tRC) (note1)
;	000 = 1 cycle 001 = 2 cycles
;	010 = 3 cycles 011 = 4 cycles
;	100 = 5 cycles 101 = Not used (6 cycles)
;	110 = Not used 111 = Not used
;[20] CAS setup time (tCSR) (note2)
;	0 = 1 cycle
;	1 = 2 cycles
;[31:21] Refresh count value (duration)
;	The refresh period is calculated as (2 11 - Value + 1) / f MCLK

REF_SADDR	DEFINE	0x3F0
REF_VSF		DEFINE	1	; Accessible to memory bank	
REF_REN		DEFINE	1	; Enable DRAM refresh
REF_TCHR	DEFINE	4	; 5 cycles(CAS hold time)
REF_TCSR	DEFINE	0	; 1 cycles(CAS setup tim)
REF_CNT		DEFINE	0x4E1	; Refresh count value