/*********************************************************************
;* Project Name : s3c2443x
;*
;* Copyright 2006 by Samsung Electronics, Inc.
;* All rights reserved.
;*
;* Project Description :
;* This software is only for verifying functions of the s3c2443x
;* Anybody can use this code without our permission.
;**********************************************************************/

#ifndef __DISPLAY_H__
#define __DISPLAY_H__

#ifdef __cplusplus
extern "C" {
#endif
/*
#include "Def.h"

#define LCD_FRAME_BUFFER		_NONCACHE_STARTADDRESS

#define LCD_WIN0_FRAME_BUFFER		LCD_FRAME_BUFFER
#define LCD_WIN1_FRAME_BUFFER		(LCD_WIN0_FRAME_BUFFER+0x100000)

#define LCD_DELAY_300NS	54		//on the basis of 540MHz
#define LCD_DELAY_50US	9000	//on the basis of 540MHz
*/
#define LCD_DELAY_1MS	1000	//180000	//on the basis of 540MHz

#define LCD_MODULE_LTS222	1
#define LCD_MODULE_LTV350	2

#define LCD_MODULE_TYPE 	LCD_MODULE_LTV350

//* SPECIFIC FOR LTS222 MODULE
#define LTS222_VBPD		(9)		
#define LTS222_VFPD		(10)
#define LTS222_VSPW		(3)
#define LTS222_HBPD		(1)		
#define LTS222_HFPD		(6)
#define LTS222_HSPW		(3)
#define LTS222_HOZVAL	(240)
#define LTS222_LINEVAL	(320)

#define LTS222_FRAME_RATE	65

//* SPECIFIC FOR LTV350 MODULE
#define LTV350_VBPD		(5)
#define LTV350_VFPD		(3)
#define LTV350_VSPW		(4)
#define LTV350_HBPD		(5)
#define LTV350_HFPD		(3)
#define LTV350_HSPW		(10)
#define LTV350_HOZVAL	(320)
#define LTV350_LINEVAL	(240)

#define LTV350_FRAME_RATE	65

//* VIDCON0	
#define VIDCON0_S_RGB_IF					(0<<22)
#define VIDCON0_S_RGB_PAR					(0<<13)
#define VIDCON0_S_BGR_PAR					(1<<13)
#define VIDCON0_S_CLKVAL_F_AlWAYS_UPDATE	(0<<12)
#define VIDCON0_S_CLKVAL_F_SOF_UPDATE		(1<<12)
#define VIDCON0_S_VCLK_GATING_ON			(0<<5)
#define VIDCON0_S_VCLK_GATING_OFF			(1<<5)
#define VIDCON0_S_CLKDIR_DIRECT				(0<<4)
#define VIDCON0_S_CLKDIR_DIVIDED			(1<<4)
#define VIDCON0_S_CLKSEL_HCLK				(0<<2)
#define VIDCON0_S_CLKSEL_UPLL				(1<<2)
#define VIDCON0_S_ENVID_OFF					(0<<1)
#define VIDCON0_S_EVVID_ON					(1<<1)
#define VIDCON0_S_ENVID_F_OFF				(0<<0)
#define VIDCON0_S_ENVID_F_ON				(1<<0)
//bit shift
#define VIDCON0_CLKVAL_F_SHIFT				(6)

//* VIDCON1
#define VIDCON1_S_VCLK_FALL_EDGE_FETCH		(0<<7)
#define VIDCON1_S_VCLK_RISE_EDGE_FETCH		(1<<7)
#define VIDCON1_S_HSYNC_INVERTED			(1<<6)
#define VIDCON1_S_VSYNC_INVERTED			(1<<5)
#define VIDCON1_S_VDEN_INVERTED				(1<<4)


//* VIDTCON0,1
//bit shift
#define VIDTCON0_BPD_S				(16)
#define VIDTCON0_FPD_S				(8)
#define VIDTCON0_SPW_S				(0)

//* VIDTCON2
//bit shift
#define VIDTCON2_LINEVAL_S			(11)
#define VIDTCON2_HOZVAL_S			(0)
/*
//* WINCON0
//shift
#define WINCON0_INRGB_S				(13)
*/
//* WINCON1to4
#define WINCONx_BIT_SWAP_ON			(1<<2)	//shift on basis of half-word swap
#define WINCONx_BYTE_SWAP_ON		(1<<1)	//shift on basis of half-word swap
#define WINCONx_HALFW_SWAP_ON		(1<<0)	//shift on basis of half-word swap
#define WINCONx_4WORD_BURST			(2)
#define WINCONx_8WORD_BURST			(1)
#define WINCONx_16WORD_BURST		(0)
#define WINCONx_PLANE_BLENDING		(0)
#define WINCONx_PIXEL_BLENDING		(1)
#define WINCONx_1BPP_PALLET			(0)
#define WINCONx_2BPP_PALLET			(1)
#define WINCONx_4BPP_PALLET			(2)
#define WINCONx_8BPP_PALLET			(3)
#define WINCONx_8BPP_NO_PALLET		(4)
#define WINCONx_16BPP_565			(5)
#define WINCONx_16BPP_A555			(6)
#define WINCONx_16BPP_1555			(7)
#define WINCONx_18BPP_666			(8)
#define WINCONx_18BPP_A665			(9)
#define WINCONx_19BPP_A666			(10)
#define WINCONx_24BPP_888			(11)
#define WINCONx_24BPP_A887			(12)
#define WINCONx_25BPP_A888			(13)
#define WINCONx_ALPHA_MODE_0		(0)
#define WINCONx_ALPHA_MODE_1		(1)


//bit shift
#define WINCON_SWAP_S				(16)
#define WINCON_BURSTLEN_S			(9)
#define WINCON_BLENDING_S			(6)
#define WINCON_BPP_S				(2)
#define WINCON_ALPHA_S				(1)

//* VIDWxADD2
//bit shift
#define VIDWxADD2_OFFSET_SIZE_S		(13)
#define VIDWxADD2_PAGE_WIDTH_S		(0)

//* VIDOSDxA,B,C
//bit shift
#define VIDOSDxAB_HORIZON_X_S		(11)
#define VIDOSDxAB_VERTICAL_Y_S		(0)
#define VIDOSDxC_ALPHA0_S		(12)

/*
#define LCD_WIN_0					0
#define LCD_WIN_1					1
#define LCD_WIN_2					2
#define LCD_WIN_3					3
#define LCD_WIN_4					4
#define LCD_WIN_ALL					5

#define LCD_OFF						0
#define LCD_ON						1


	// set spi for lcd 
	// 1. set jumper like as 1-2 in J15 at SMDK board
	// 2. you can use the SPI1 to control LCD sfr register
	// nSS1 		---> SPI_LCDnSS  	---> GPL 14
	// SPIMOSI1	---> SPI_LCDMOSI      ---> GPL 11
	// SPICLK1    ---> SPI_LCDCLK        ---> GPL 10
*/
#define LCD_DEN		(1<<14)
#define LCD_DSERI	(1<<11)
#define LCD_DCLK	(1<<10)

#define LCD_DEN_BIT		14
#define LCD_DSERI_BIT	11
#define LCD_DCLK_BIT	10

#define LCD_nRESET		1



//#define LCD_RESET     (0)

//#if 1	//org.
#define LCD_DEN_Lo		(s2443IOP->GPLDAT &= ~LCD_DEN)
#define LCD_DEN_Hi		(s2443IOP->GPLDAT |=	LCD_DEN)
#define LCD_DCLK_Lo		(s2443IOP->GPLDAT &= ~LCD_DCLK)
#define LCD_DCLK_Hi		(s2443IOP->GPLDAT |=	LCD_DCLK)
#define LCD_DSERI_Lo	(s2443IOP->GPLDAT &= ~LCD_DSERI)
#define LCD_DSERI_Hi	(s2443IOP->GPLDAT |=	LCD_DSERI)
/*
#else	//specific for mDirac3
#define LCD_DEN_Lo	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT &= ~LCD_DEN; \
	rGPFDAT = var_GPFDAT; \
}
#define LCD_DEN_Hi	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT |= LCD_DEN; \
	rGPFDAT = var_GPFDAT; \
}
#define LCD_DCLK_Lo	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT &= ~LCD_DCLK; \
	rGPFDAT = var_GPFDAT; \
}
#define LCD_DCLK_Hi	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT |= LCD_DCLK; \
	rGPFDAT = var_GPFDAT; \
}
#define LCD_DSERI_Lo	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT &= ~LCD_DSERI; \
	rGPFDAT = var_GPFDAT; \
}
#define LCD_DSERI_Hi	\
{ \
	extern uint32 var_GPFDAT; \
	var_GPFDAT |= LCD_DSERI; \
	rGPFDAT = var_GPFDAT; \
}
#endif

#define LCD_RESET_Lo	(0)
#define LCD_RESET_Hi	(1)


*/
#endif //#ifndef __DISPLAY_H__