?? sp_serialflashv1.lst
字號(hào):
// Used register: r1,r2,r3,r4
// Return register: r1
//////////////////////////////////////////////////////////////////
.public _SP_SIOReadAWord;
_SP_SIOReadAWord: .PROC
F_SIOReadAWord:
00008136 88 DA PUSH BP,BP TO [SP];
00008137 08 0B 01 00 BP = SP + 1;
00008139 0C 99 FF 00 r4=0x00FF;
0000813B 03 92 R1 = [BP+3];
0000813C 19 D3 1B 70 [P_SIO_Addr_Low]=r1; // input SFLASH low address
0000813E 79 93 r1=r1 lsr 4;
0000813F 79 93 r1=r1 lsr 4;
00008140 19 D3 1C 70 [P_SIO_Addr_Mid]=r1; // input SFLASH mid address
00008142 04 92 R1 = [BP+4]; // Port direction
00008143 47 B2 r1=r1&0x0007; // input SFLASH hi address
00008144 19 D3 1D 70 [P_SIO_Addr_High]=r1;
00008146 09 93 83 00 r1=0x0083; //+C_SIOCLOCK; // C_SIOCLOCK 0x0010
00008148 19 D3 1E 70 [P_SIO_Ctrl]=r1; // clk=CPUclk/16, 24 bit address ;read
0000814A 19 D3 1F 70 [P_SIO_Start]=r1; // enable read mode
0000814C 12 95 1A 70 r2=[P_SIO_Data]; // Clear SFLASH buffer
L_WaitSIOReadReady1LB:
0000814E 11 93 1F 70 r1=[P_SIO_Start];
00008150 09 C3 80 00 test r1,0x0080
00008152 45 4E jnz L_WaitSIOReadReady1LB
00008153 14 B5 1A 70 r2=r4&[P_SIO_Data]; // Read exact Low Byte
L_WaitSIOReadReady2LB: // Wait read stop
00008155 11 93 1F 70 r1=[P_SIO_Start];
00008157 09 C3 80 00 test r1,0x0080
00008159 45 4E jnz L_WaitSIOReadReady2LB
0000815A 14 B7 1A 70 r3=r4&[P_SIO_Data]; // Read exact High Byte
L_WaitSIOReadReady2HB: // Wait read stop
0000815C 11 93 1F 70 r1=[P_SIO_Start];
0000815E 09 C3 80 00 test r1,0x0080
00008160 45 4E jnz L_WaitSIOReadReady2HB
00008161 19 D3 20 70 [P_SIO_Stop]=r1; // disable read mode
00008163 5B 97 r3=r3 lsl 4; //shift left 8
00008164 5B 93 r1=r3 lsl 4;
00008165 02 A3 r1|=r2; //return data
00008166 88 98 POP BP,BP FROM [SP];
00008167 90 9A retf;
.ENDP;
///////////////////////////////////////////////////////////////
//Function : Mass Erase for S_Flash
// Syntax: SIOMassErase()
// Used register: r1,r2
///////////////////////////////////////////////////////////////
.public _SP_SIOMassErase;
_SP_SIOMassErase: .PROC
F_SIOMassErase:
00008168 90 D4 push r1,r2 to [sp];
00008169 09 93 D0 00 r1=0x00C0+C_SIOCLOCK;
0000816B 19 D3 1E 70 [P_SIO_Ctrl]=r1; // clk=CPUclk/8, 16 bit address ;write
0000816D 40 94 r2=0x0000;
0000816E 1A D5 1B 70 [P_SIO_Addr_Low]=r2; // input SFLASH low address
00008170 0A 95 C0 00 r2=0x00C0;
00008172 1A D5 1C 70 [P_SIO_Addr_Mid]=r2; // input SFLASH mid address
00008174 0A 95 C0 00 r2=0x00C0;
00008176 1A D5 1D 70 [P_SIO_Addr_High]=r2;
// r1=0x00C0+C_SIOCLOCK;
// [P_SIO_Ctrl]=r1; // clk=CPUclk/8, 16 bit address ;write
00008178 19 D3 1F 70 [P_SIO_Start]=r1; // enable write mode
0000817A 40 92 r1=0; // A7~A0 = 0
0000817B 19 D3 1A 70 [P_SIO_Data]=r1; // state to transmit data
L_WaitSIOSendReadyMass:
0000817D 11 93 1F 70 r1=[P_SIO_Start];
0000817F 09 C3 80 00 test r1,0x0080
00008181 45 4E jnz L_WaitSIOSendReadyMass
//disable write mode
00008182 19 D3 20 70 [P_SIO_Stop]=r1;
00008184 40 F0 8E 81 call F_Delay11ms
00008186 40 F0 8E 81 call F_Delay11ms //modify by abin
00008188 40 F0 8E 81 call F_Delay11ms
0000818A 40 F0 8E 81 call F_Delay11ms
0000818C 90 90 pop r1,r2 from [sp];
0000818D 90 9A retf;
.ENDP;
F_Delay11ms:
0000818E 88 D2 push r1,r1 to [sp];
//r1=17*10;
0000818F 09 93 C8 00 r1=20*10; // delay
L_LoopDelay11:
00008191 40 F0 97 81 call F_Delay100uS;
00008193 41 22 r1-=1;
00008194 44 4E jne L_LoopDelay11
00008195 88 90 pop r1,r1 from [sp];
00008196 90 9A retf;
///////////////////////////////////////////////////////////////
//Function : 100us Dealy for S_Flash programming time (base on CPUCLK= 24MHz)
// Syntax: Delay100uS()
// Used register: r1,r2
///////////////////////////////////////////////////////////////
.public _Delay100uS;
_Delay100uS: .PROC
F_Delay100uS: //13
00008197 88 D2 push r1,r1 to [sp]; //7
00008198 09 93 26 01 r1=294; //6
L_DelayLoop:
0000819A 41 22 r1-=1; //3 26+19+8*294 =2400
0000819B 42 4E jne L_DelayLoop; //5
0000819C 88 90 pop r1,r1 from [sp]; //7
0000819D 90 9A retf; //12
.ENDP;
///////////////////////////////////////////////////////////////
//Function : Dealy for S_Flash programming time (base on CPUCLK= 24MHz)
// Syntax: DelayPT()
// Used register: r1
///////////////////////////////////////////////////////////////
.public _DelayPT;
_DelayPT: .PROC
F_DelayPT: //13
0000819E 88 D2 push r1,r1 to [sp]; //7
//r1=294; //6
//r1=147;
//r1=1600;
//r1=100;
0000819F 09 93 A0 00 r1=160
//r1=200;
L_DelayLoopPT:
000081A1 41 22 r1-=1; //3 26+19+8*160 =1325 ----> 56us
000081A2 42 4E jne L_DelayLoopPT; //5
000081A3 88 90 pop r1,r1 from [sp]; //7
000081A4 90 9A retf; //12
.ENDP;
///////////////////////////////////////////////////////////////
//Function : Page Erase for S_Flash (Page Size 1K)
// Syntax: SP_SIOSectorErase(Sector)
// Used register: r1,r2
///////////////////////////////////////////////////////////////
.public _SP_SIOSectorErase;
_SP_SIOSectorErase: .PROC
SP_SIOSectorErase:
000081A5 88 DA PUSH BP,BP TO [SP];
000081A6 08 0B 01 00 BP = SP + 1;
000081A8 03 92 R1 = [BP+3];
000081A9 09 B3 FF 00 r1=r1&0x00ff;
000081AB 51 93 r1=r1 lsl 3;
000081AC 09 A3 00 80 r1=r1|0x8000;
000081AE 19 D3 1B 70 [P_SIO_Addr_Low]=r1; // input SFLASH low address ;for A15 and A10
000081B0 79 93 r1=r1 lsr 4;
000081B1 79 93 r1=r1 lsr 4;
000081B2 19 D3 1C 70 [P_SIO_Addr_Mid]=r1; // input SFLASH mid address ;for A16
000081B4 09 93 D0 00 r1=0x00C0+C_SIOCLOCK;
000081B6 19 D3 1E 70 [P_SIO_Ctrl]=r1; // clk=CPUclk/8, 16 bit address ;write
000081B8 19 D3 1F 70 [P_SIO_Start]=r1; // enable write mode
000081BA 40 92 r1=0; // A7~A0 = 0
000081BB 19 D3 1A 70 [P_SIO_Data]=r1; // state to transmit data
L_WaitSIOSendReadyPage1:
000081BD 11 93 1F 70 r1=[P_SIO_Start];
000081BF 09 C3 80 00 test r1,0x0080
000081C1 45 4E jnz L_WaitSIOSendReadyPage1
000081C2 19 D3 20 70 [P_SIO_Stop]=r1; //disable write mode
000081C4 40 F0 8E 81 call F_Delay11ms
000081C6 88 98 POP BP,BP FROM [SP];
000081C7 90 9A retf;
.ENDP;
0 error(s), 0 warning(s).
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