;**************************************************************
; MODULE : register.a 
; PURPOSE : Define the register address of each module
; written by CES
; VERSION : Versio 0.1
; 12/11/2000
;**************************************************************

ASICBase      EQU     0x0C000000		; register's base address
AHBSEL        EQU     0x0D000000        ; AHB address area
SCRBase	      EQU     0x40000000		; System Configuration register address

; define the base of each I/O devices
ARM920T       EQU     ASICBase              ; ARM920T   
MEMBase       EQU     ASICBase + 0x10000    ; Memory controller
DMABase       EQU     ASICBase + 0x20000    ; DMA controller 
LCDBase       EQU     ASICBase + 0x30000    ; LCD controller 
EMACBase      EQU     ASICBase + 0x40000    ; Ethernet MAC controller 
XMEMBase      EQU     ASICBase + 0x50000
YMEMBase      EQU     ASICBase + 0x60000
PMEMBase      EQU     ASICBase + 0x70000
APBBase	      EQU     ASICBase + 0x80000    ; AHB2APB bridge 

; define the base of each APB Bridge devices
WDTBase       EQU     APBBase  + 0x1C00    ; Watch dog timer
IOPBase       EQU     APBBase  + 0x2000    ; GPIO
INTBase       EQU     APBBase  + 0x2800    ; Interrupt controller
PMBase        EQU     APBBase  + 0x3C00    ; Power manager

; Memory Controller 
SDRAMCFG0     EQU     MEMBase+0x00      ; SDRAM config0 register
SDRAMCFG1     EQU     MEMBase+0x04      ; SDRAM config1 register 
SDRAMRefresh  EQU     MEMBase+0x08      ; SDRAM refresh register 
SDRAMWB       EQU     MEMBase+0x0C      ; SDRAM WB timeout register 
;old version
SRAMCFG       EQU     MEMBase+0x400      
ROMCFG        EQU     MEMBase+0x404
FLASHCFG      EQU     MEMBase+0x408
BANKCFG       EQU     MEMBase+0x40C
;new version
SMCBANK0      EQU     MEMBase+0x10      
SMCBANK1      EQU     MEMBase+0x14
SMCBANK2      EQU     MEMBase+0x18
SMCBANK3      EQU     MEMBase+0x1C

; Clock & Power management
PLLCON        EQU     PMBase + 0x00    ; pll configuration register 
MODCON        EQU     PMBase + 0x04    ; mode control register
HCLKCON       EQU     PMBase + 0x08    ; AHB clock control register
PCLKCON       EQU     PMBase + 0x0C    ; APB clock control register

; Watch dog timer register address
WDTMOD        EQU     WDTBase+0x00

; GPIO register address
GIOPCON       EQU     IOPBase+0x00
GIOPDATA      EQU     IOPBase+0x04
GIOPINTEN     EQU     IOPBase+0x08
GIOPLEVEL     EQU     IOPBase+0x0C
GIOPPEND      EQU     IOPBase+0x10

; Interrupt controller register address
INTCON	      EQU     INTBase+0x00
INTPND	      EQU     INTBase+0x04
INTMOD	      EQU     INTBase+0x08
INTMSK	      EQU     INTBase+0x0C
INTLEVEL      EQU     INTBase+0x10

IRQPSLV0      EQU     INTBase+0x14
IRQPSLV1      EQU     INTBase+0x18
IRQPSLV2      EQU     INTBase+0x1C
IRQPSLV3      EQU     INTBase+0x20
IRQPMST	      EQU     INTBase+0x24
IRQCSLV0      EQU     INTBase+0x28
IRQCSLV1      EQU     INTBase+0x2C
IRQCSLV2      EQU     INTBase+0x30
IRQCSLV3      EQU     INTBase+0x34
IRQCMST	      EQU     INTBase+0x38
IRQISPR	      EQU     INTBase+0x3C
IRQISPC	      EQU     INTBase+0x40

FIQPSLV0      EQU     INTBase+0x44
FIQPSLV1      EQU     INTBase+0x48
FIQPSLV2      EQU     INTBase+0x4C
FIQPSLV3      EQU     INTBase+0x50
FIQPMST	      EQU     INTBase+0x54
FIQCSLV0      EQU     INTBase+0x58
FIQCSLV1      EQU     INTBase+0x5C
FIQCSLV2      EQU     INTBase+0x60
FIQCSLV3      EQU     INTBase+0x64
FIQCMST	      EQU     INTBase+0x68
FIQISPR	      EQU     INTBase+0x6C
FIQISPC	      EQU     INTBase+0x70

POLARITY      EQU     INTBase+0x74
IVEC_ADDR     EQU     INTBase+0x78
FVEC_ADDR     EQU     INTBase+0x7C
	END