?? vectors.s
字號:
;************************************************************************
; MODULE : vectors.s *
; PURPOSE : ARM Specific Exception Vector Setting Sub. Routines. *
; VERSION : Version 0.1 *
; 12/11/2000 *
;************************************************************************
GET lolevel.a
GET register.a
EXPORT UNDEFHandler ; Undefined instruction
EXPORT SWIHandler ; SWI
EXPORT pABORTHandler ; Prefetch abort
EXPORT dABORTHandler ; Data abort
EXPORT IRQHandler ; IRQ
IMPORT Uart_Printf
GBLL VECTOR
VECTOR SETL {TRUE}
AREA |ExceptHandler|, CODE, READONLY
;************************************************************************
; IRQHandler
;************************************************************************
IRQHandler
SUB lr, lr, #4 ; Construct the return address
STMFD sp!, {lr} ; and push the adjusted lr_IRQ
MRS r14, SPSR ; copy spsr_IRQ to r14
STMFD sp!, {r0-r12, r14} ; save work registers and spsr_IRQ
GetIrqSource
[ :LNOT:VECTOR
LDR r1, =IRQISPR ;read interrupt pending register(IRQ)
LDR r1, [r1]
MOV r2, #0 ; non-vectored
0 MOVS r1, r1, LSR #1
BCS %F1
ADD r2, r2, #4
B %B0
|
LDR r1, =IVEC_ADDR ; semi vectored address register
LDR r2, [r1]
]
1 LDR r3, =IntVectorTable
ADD r3, r3, r2
LDR r3, [r3]
; It is assumed that the handler function called will execute
; within the interrupt handler stack allocation, and the code
; will not manipulate the interrupt mask status, or the SPSR
; register:
LDR lr, =ReturnFromIRQService ; generate return address
MOV pc, r3 ; call handler function
ReturnFromIRQService
; We won't have interrupted an FIQ, so r0-r12 will not be banked
; so we have to reinstate these before returning.
; Assume that SPSR has not been corrupted.
LDMFD sp!, {r0-r12, r14} ; Restore work registers and spsr_IRQ
MSR spsr_cf, r14
LDMFD sp!, {pc}^ ; return from IRQ
;************************************************************************
; UNDEFHandler
;************************************************************************
UNDEFHandler
STMFD sp!, {r0-r12, lr} ; store registers
; Call undefine exception service routine or execute the undefine exception service
LDR r0, =MsgError0
BL Uart_Printf
;
LDMFD sp!, {r0-r12, lr} ; store registers
;************************************************************************
; SWIHandler
;************************************************************************
SWIHandler
STMFD sp!, {r0-r12, lr} ; store registers
LDR r0, [lr, #-4] ; caculate address of SWI instruction
BIC r0, r0, #0xff000000 ; Mask off top 8 bits of instruction to give SWI number
; Use value in r0 to determine which SWI routine to execute.
LDMFD sp!, {r0-r12, pc}^ ; store registers
;************************************************************************
; Prefetch abort handler
;************************************************************************
pABORTHandler
SUB lr, lr, #4 ; Construct the return address
STMFD sp!, {lr} ; and push the adjusted lr_IRQ
MRS r14, SPSR ; copy spsr_IRQ to r14
STMFD sp!, {r0-r12, r14} ; save work registers and spsr_IRQ
; Call abort service routine or execute the abort service
LDR r0, =MsgError1
BL Uart_Printf
;
LDMFD sp!, {r0-r12, r14} ; Restore work registers and spsr_IRQ
MSR spsr_cf, r14
LDMFD sp!, {pc}^ ; return from IRQ
;************************************************************************
; DATA abort handler
;************************************************************************
dABORTHandler
SUB lr, lr, #8 ; Construct the return address
STMFD sp!, {lr} ; and push the adjusted lr_IRQ
MRS r14, SPSR ; copy spsr_IRQ to r14
STMFD sp!, {r0-r12, r14} ; save work registers and spsr_IRQ
; Call abort service routine or execute the abort service
LDR r0, =MsgError2
BL Uart_Printf
;
LDMFD sp!, {r0-r12, r14} ; Restore work registers and spsr_IRQ
MSR spsr_cf, r14
LDMFD sp!, {pc}^ ; return from IRQ
AREA ROMData1, DATA, READONLY
MsgError0 DCB "System Error!(Undefined) \n",0
MsgError1 DCB "System Error!(pAbort) \n",0
MsgError2 DCB "System Error!(dAbort) \n",0
END
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