;/**
;* Project Name : S3C2460 verification project
;*
;* Copyright 2004 by Samsung Electronics, Inc.
;* All rights reserved.
;*
;* Project Description :
;* This software is only for verifying functions of the S3C2460. 
;* Anybody can use this code without our permission.
;*/

;/**
;* File Name    : 2460init.s
;* Description  : S3C2460 startup code
;* Author       : Y.C.Kwon
;* Dept         : Mobile solution, AP
;* Created Date : 2004.09.16
;* Version      : 0.0
;* History
;*   R0.0 (2004.09.16): Kwon draft
;*/

				GET		Option.inc
				GET		2460addr.inc

				MACRO
$HandlerLabel 	HANDLER		$HandleLabel

$HandlerLabel
				sub		sp,sp,#4        	;decrement sp(to store jump address)
				stmfd	sp!,{r0}        	;PUSH the work register to stack(lr doesnt push because it return to original address)
				ldr     r0,=$HandleLabel	;load the address of HandleXXX to r0
				ldr     r0,[r0]         	;load the contents(service routine start address) of HandleXXX
				str     r0,[sp,#4]      	;store the contents(ISR) of HandleXXX to stack
				ldmfd   sp!,{r0,pc}     	;POP the work register and pc(jump to ISR)

				MEND

	[ (WHICH_PORT=1)
				IMPORT	InitPORT1
	]
				IMPORT	InitPORT2

				IMPORT  __main   			; The main entry of mon program 

				AREA    Init,CODE,READONLY

				ENTRY 

				b		ResetHandler	;handler for Reset  
				b		HandlerUndef	;handler for Undefined mode
				b		HandlerSWI		;handler for SWI interrupt
				b		HandlerPabort	;handler for PAbort
				b		HandlerDabort	;handler for DAbort
				b		.				;reserved
			    b		HandlerIRQ		;handler for IRQ interrupt 
				b		HandlerFIQ		;handler for FIQ interrupt
	
HandlerUndef	HANDLER HandleUndef
HandlerSWI		HANDLER HandleSWI
HandlerPabort	HANDLER HandlePabort
HandlerDabort	HANDLER HandleDabort
HandlerIRQ		HANDLER HandleIRQ		
HandlerFIQ		HANDLER	HandleFIQ


;=======================================================
;						ENTRY  
;=======================================================

ResetHandler

				ldr		r0,=rWTCON			;	Disable WatchDog.
				mov		r1,#0
				str		r1,[r0]			
					
				ldr		r0,=rCLKDIVCON		;	Set Clock Divider
				ldr		r1,[r0]
				bic		r1,r1,#0x10000
				bic		r1,r1,#0x7
				ldr		r2,=((Startup_ARMCLKdiv<<16)|(Startup_PCLKdiv<<2)|(Startup_HCLKdiv)) 
				orr		r1,r1,r2
				str		r1,[r0]			
	
				ldr		r0,=rLOCKTIME0		;	Set MPLL Locktime
				ldr		r1,[r0]
				orr		r1,r1,#0xff00
				orr		r1,r1,#0xff
				str		r1,[r0]			
	
				ldr		r0,=rMPLLCON		;	Set MPLL
				ldr		r1,=((Startup_Mdiv<<16)|(Startup_Pdiv<<8)|(Startup_Sdiv))
				str		r1,[r0]		

				ldr		r0,=rCLKSRCCON		;	Select MPLL clock out for SYSCLK
				ldr		r1,[r0]
				orr		r1,r1,#0x10
				str		r1,[r0]						

	[ (WHICH_PORT=1)
				bl		InitPORT1
	]
				bl		InitPORT2
				
				ldr		r0,=rSROM_BC0
				ldr		r1,=(3<<8)
				str		r1,[r0]

			   	bl		__main
			   	b		.

				LTORG


			   	ALIGN

			   	AREA IntVector, DATA, READWRITE

				^   _ISR_STARTADDRESS

HandleReset 	#   4
HandleUndef 	#   4
HandleSWI   	#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ   	#   4
HandleFIQ   	#   4

		        END