/* ************************************************************************* * Ralink Tech Inc. * 5F., No.36, Taiyuan St., Jhubei City, * Hsinchu County 302, * Taiwan, R.O.C. * * (c) Copyright 2002-2007, Ralink Technology, Inc. * * This program is free software; you can redistribute it and/or modify  *  * it under the terms of the GNU General Public License as published by  *  * the Free Software Foundation; either version 2 of the License, or     *  * (at your option) any later version.                                   *  *                                                                       *  * This program is distributed in the hope that it will be useful,       *  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *  * GNU General Public License for more details.                          *  *                                                                       *  * You should have received a copy of the GNU General Public License     *  * along with this program; if not, write to the                         *  * Free Software Foundation, Inc.,                                       *  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *  *                                                                       *  *************************************************************************	Module Name:	rt28xx.h	Abstract:	RT28xx ASIC related definition & structures	Revision History:	Who			When		  What	--------	----------	  ----------------------------------------------       Jan Lee           Jan-3-2006     created for RT2860c*/#ifndef	__RT28XX_H__#define	__RT28XX_H__//// PCI registers - base address 0x0000//#define PCI_CFG			0x0000#define PCI_EECTRL			0x0004#define PCI_MCUCTRL			0x0008#define	OPT_14			0x114typedef int				NTSTATUS;#define	RETRY_LIMIT             10#define STATUS_SUCCESS				0x00#define STATUS_UNSUCCESSFUL 		0x01//// SCH/DMA registers - base address 0x0200//// INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit//#define DMA_CSR0      0x200#define INT_SOURCE_CSR      0x200#ifdef RT_BIG_ENDIANtypedef	union	_INT_SOURCE_CSR_STRUC	{	struct	{		UINT32       	:14;		UINT32       	TxCoherent:1;		UINT32       	RxCoherent:1;		UINT32       	GPTimer:1;		UINT32       	AutoWakeup:1;//bit14		UINT32       	TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c		UINT32       	PreTBTT:1;		UINT32       	TBTTInt:1;		UINT32       	RxTxCoherent:1;		UINT32       	MCUCommandINT:1;		UINT32       	MgmtDmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32		Ac0DmaDone:1;		UINT32		RxDone:1;		UINT32		TxDelayINT:1;	//delayed interrupt, not interrupt until several int or time limit hit		UINT32		RxDelayINT:1; //dealyed interrupt	}	field;	UINT32			word;}	INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;#elsetypedef	union	_INT_SOURCE_CSR_STRUC	{	struct	{		UINT32		RxDelayINT:1;		UINT32		TxDelayINT:1;		UINT32		RxDone:1;		UINT32		Ac0DmaDone:1;//4      		UINT32       	Ac1DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	HccaDmaDone:1; // bit7		UINT32       	MgmtDmaDone:1;		UINT32       	MCUCommandINT:1;//bit 9		UINT32       	RxTxCoherent:1;		UINT32       	TBTTInt:1;		UINT32       	PreTBTT:1;		UINT32       	TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c		UINT32       	AutoWakeup:1;//bit14		UINT32       	GPTimer:1;		UINT32       	RxCoherent:1;//bit16		UINT32       	TxCoherent:1;		UINT32       	:14;	}	field;	UINT32			word;} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;#endif//// INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF//#define INT_MASK_CSR        0x204#ifdef RT_BIG_ENDIANtypedef	union	_INT_MASK_CSR_STRUC	{	struct	{		UINT32       	TxCoherent:1;		UINT32       	RxCoherent:1;		UINT32       	:20;		UINT32       	MCUCommandINT:1;		UINT32       	MgmtDmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32		Ac0DmaDone:1;		UINT32		RxDone:1;		UINT32		TxDelay:1;		UINT32		RXDelay_INT_MSK:1;	}	field;	UINT32			word;}INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;#elsetypedef	union	_INT_MASK_CSR_STRUC	{	struct	{		UINT32		RXDelay_INT_MSK:1;		UINT32		TxDelay:1;		UINT32		RxDone:1;		UINT32		Ac0DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	MgmtDmaDone:1;		UINT32       	MCUCommandINT:1;		UINT32       	:20;		UINT32       	RxCoherent:1;		UINT32       	TxCoherent:1;	}	field;	UINT32			word;} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;#endif#define WPDMA_GLO_CFG 	0x208#ifdef RT_BIG_ENDIANtypedef	union	_WPDMA_GLO_CFG_STRUC	{	struct	{		UINT32       	HDR_SEG_LEN:16;		UINT32       	RXHdrScater:8;		UINT32       	BigEndian:1;		UINT32       	EnTXWriteBackDDONE:1;		UINT32       	WPDMABurstSIZE:2;		UINT32		RxDMABusy:1;		UINT32		EnableRxDMA:1;		UINT32		TxDMABusy:1;		UINT32		EnableTxDMA:1;	}	field;	UINT32			word;}WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;#elsetypedef	union	_WPDMA_GLO_CFG_STRUC	{	struct	{		UINT32		EnableTxDMA:1;		UINT32		TxDMABusy:1;		UINT32		EnableRxDMA:1;		UINT32		RxDMABusy:1;		UINT32       	WPDMABurstSIZE:2;		UINT32       	EnTXWriteBackDDONE:1;		UINT32       	BigEndian:1;		UINT32       	RXHdrScater:8;		UINT32       	HDR_SEG_LEN:16;	}	field;	UINT32			word;} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;#endif#define WPDMA_RST_IDX 	0x20c#ifdef RT_BIG_ENDIANtypedef	union	_WPDMA_RST_IDX_STRUC	{	struct	{		UINT32       	:15;		UINT32       	RST_DRX_IDX0:1;		UINT32       	rsv:10;		UINT32       	RST_DTX_IDX5:1;		UINT32       	RST_DTX_IDX4:1;		UINT32		RST_DTX_IDX3:1;		UINT32		RST_DTX_IDX2:1;		UINT32		RST_DTX_IDX1:1;		UINT32		RST_DTX_IDX0:1;	}	field;	UINT32			word;}WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;#elsetypedef	union	_WPDMA_RST_IDX_STRUC	{	struct	{		UINT32		RST_DTX_IDX0:1;		UINT32		RST_DTX_IDX1:1;		UINT32		RST_DTX_IDX2:1;		UINT32		RST_DTX_IDX3:1;		UINT32       	RST_DTX_IDX4:1;		UINT32       	RST_DTX_IDX5:1;		UINT32       	rsv:10;		UINT32       	RST_DRX_IDX0:1;		UINT32       	:15;	}	field;	UINT32			word;} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;#endif#define DELAY_INT_CFG  0x0210#ifdef RT_BIG_ENDIANtypedef	union	_DELAY_INT_CFG_STRUC	{	struct	{		UINT32       	TXDLY_INT_EN:1;		UINT32       	TXMAX_PINT:7;		UINT32       	TXMAX_PTIME:8;		UINT32       	RXDLY_INT_EN:1;		UINT32       	RXMAX_PINT:7;		UINT32		RXMAX_PTIME:8;	}	field;	UINT32			word;}DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;#elsetypedef	union	_DELAY_INT_CFG_STRUC	{	struct	{		UINT32		RXMAX_PTIME:8;		UINT32       	RXMAX_PINT:7;		UINT32       	RXDLY_INT_EN:1;		UINT32       	TXMAX_PTIME:8;		UINT32       	TXMAX_PINT:7;		UINT32       	TXDLY_INT_EN:1;	}	field;	UINT32			word;} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;#endif#define WMM_AIFSN_CFG   0x0214#ifdef RT_BIG_ENDIANtypedef	union	_AIFSN_CSR_STRUC	{	struct	{	    UINT32   Rsv:16;	    UINT32   Aifsn3:4;       // for AC_VO	    UINT32   Aifsn2:4;       // for AC_VI	    UINT32   Aifsn1:4;       // for AC_BK	    UINT32   Aifsn0:4;       // for AC_BE	}	field;	UINT32			word;}	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;#elsetypedef	union	_AIFSN_CSR_STRUC	{	struct	{	    UINT32   Aifsn0:4;       // for AC_BE	    UINT32   Aifsn1:4;       // for AC_BK	    UINT32   Aifsn2:4;       // for AC_VI	    UINT32   Aifsn3:4;       // for AC_VO	    UINT32   Rsv:16;	}	field;	UINT32			word;}	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;#endif//// CWMIN_CSR: CWmin for each EDCA AC//#define WMM_CWMIN_CFG   0x0218#ifdef RT_BIG_ENDIANtypedef	union	_CWMIN_CSR_STRUC	{	struct	{	    UINT32   Rsv:16;	    UINT32   Cwmin3:4;       // for AC_VO	    UINT32   Cwmin2:4;       // for AC_VI	    UINT32   Cwmin1:4;       // for AC_BK	    UINT32   Cwmin0:4;       // for AC_BE	}	field;	UINT32			word;}	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;#elsetypedef	union	_CWMIN_CSR_STRUC	{	struct	{	    UINT32   Cwmin0:4;       // for AC_BE	    UINT32   Cwmin1:4;       // for AC_BK	    UINT32   Cwmin2:4;       // for AC_VI	    UINT32   Cwmin3:4;       // for AC_VO	    UINT32   Rsv:16;	}	field;	UINT32			word;}	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;#endif//// CWMAX_CSR: CWmin for each EDCA AC//#define WMM_CWMAX_CFG   0x021c#ifdef RT_BIG_ENDIANtypedef	union	_CWMAX_CSR_STRUC	{	struct	{	    UINT32   Rsv:16;	    UINT32   Cwmax3:4;       // for AC_VO	    UINT32   Cwmax2:4;       // for AC_VI	    UINT32   Cwmax1:4;       // for AC_BK	    UINT32   Cwmax0:4;       // for AC_BE	}	field;	UINT32			word;}	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;#elsetypedef	union	_CWMAX_CSR_STRUC	{	struct	{	    UINT32   Cwmax0:4;       // for AC_BE	    UINT32   Cwmax1:4;       // for AC_BK	    UINT32   Cwmax2:4;       // for AC_VI	    UINT32   Cwmax3:4;       // for AC_VO	    UINT32   Rsv:16;	}	field;	UINT32			word;}	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;#endif//// AC_TXOP_CSR0: AC_BK/AC_BE TXOP register//#define WMM_TXOP0_CFG    0x0220#ifdef RT_BIG_ENDIANtypedef	union	_AC_TXOP_CSR0_STRUC	{	struct	{	    USHORT  Ac1Txop;        // for AC_BE, in unit of 32us	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us	}	field;	UINT32			word;}	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;#elsetypedef	union	_AC_TXOP_CSR0_STRUC	{	struct	{	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us	    USHORT  Ac1Txop;        // for AC_BE, in unit of 32us	}	field;	UINT32			word;}	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;#endif//// AC_TXOP_CSR1: AC_VO/AC_VI TXOP register//#define WMM_TXOP1_CFG    0x0224#ifdef RT_BIG_ENDIANtypedef	union	_AC_TXOP_CSR1_STRUC	{	struct	{	    USHORT  Ac3Txop;        // for AC_VO, in unit of 32us	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us	}	field;	UINT32			word;}	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;#elsetypedef	union	_AC_TXOP_CSR1_STRUC	{	struct	{	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us	    USHORT  Ac3Txop;        // for AC_VO, in unit of 32us	}	field;	UINT32			word;}	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;#endif#define RINGREG_DIFF			0x10#define GPIO_CTRL_CFG    0x0228	//MAC_CSR13#define MCU_CMD_CFG    0x022c#define TX_BASE_PTR0     0x0230	//AC_BK base address#define TX_MAX_CNT0      0x0234#define TX_CTX_IDX0       0x0238#define TX_DTX_IDX0      0x023c#define TX_BASE_PTR1     0x0240 	//AC_BE base address#define TX_MAX_CNT1      0x0244#define TX_CTX_IDX1       0x0248#define TX_DTX_IDX1      0x024c#define TX_BASE_PTR2     0x0250 	//AC_VI base address#define TX_MAX_CNT2      0x0254#define TX_CTX_IDX2       0x0258#define TX_DTX_IDX2      0x025c#define TX_BASE_PTR3     0x0260 	//AC_VO base address#define TX_MAX_CNT3      0x0264#define TX_CTX_IDX3       0x0268#define TX_DTX_IDX3      0x026c#define TX_BASE_PTR4     0x0270 	//HCCA base address#define TX_MAX_CNT4      0x0274#define TX_CTX_IDX4       0x0278#define TX_DTX_IDX4      0x027c#define TX_BASE_PTR5     0x0280 	//MGMT base address#define  TX_MAX_CNT5     0x0284#define TX_CTX_IDX5       0x0288#define TX_DTX_IDX5      0x028c#define TX_MGMTMAX_CNT      TX_MAX_CNT5#define TX_MGMTCTX_IDX       TX_CTX_IDX5#define TX_MGMTDTX_IDX      TX_DTX_IDX5#define RX_BASE_PTR     0x0290 	//RX base address#define RX_MAX_CNT      0x0294#define RX_CRX_IDX       0x0298#define RX_DRX_IDX      0x029c#define USB_DMA_CFG      0x02a0#ifdef RT_BIG_ENDIANtypedef	union	_USB_DMA_CFG_STRUC	{