; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                              ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                              ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+
; qwe1.vhd                         ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/My Documents/EDA/3883/38/qwe1.vhd ;
; qwe.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Administrator/My Documents/EDA/3883/38/qwe.bdf  ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+


+--------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                              ;
+---------------------------------------------+----------------------------+
; Resource                                    ; Usage                      ;
+---------------------------------------------+----------------------------+
; Estimated Total logic elements              ; 9                          ;
; Total combinational functions               ; 9                          ;
; Logic element usage by number of LUT inputs ;                            ;
;     -- 4 input functions                    ; 0                          ;
;     -- 3 input functions                    ; 9                          ;
;     -- <=2 input functions                  ; 0                          ;
;         -- Combinational cells for routing  ; 0                          ;
; Logic elements by mode                      ;                            ;
;     -- normal mode                          ; 9                          ;
;     -- arithmetic mode                      ; 0                          ;
; Total registers                             ; 0                          ;
; I/O pins                                    ; 14                         ;
; Maximum fan-out node                        ; decoder38:inst|process0~15 ;
; Maximum fan-out                             ; 8                          ;
; Total fan-out                               ; 43                         ;
; Average fan-out                             ; 1.87                       ;
+---------------------------------------------+----------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |qwe                       ; 9 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 14   ; 0            ; |qwe                ;
;    |decoder38:inst|        ; 9 (9)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qwe|decoder38:inst ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Apr 23 11:13:00 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qwe -c qwe
Info: Found 2 design units, including 1 entities, in source file qwe1.vhd
    Info: Found design unit 1: decoder38-code1
    Info: Found entity 1: decoder38
Info: Found 1 design units, including 1 entities, in source file qwe.bdf
    Info: Found entity 1: qwe
Info: Elaborating entity "qwe" for the top level hierarchy
Info: Elaborating entity "decoder38" for hierarchy "decoder38:inst"
Info: Implemented 23 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 8 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Apr 23 11:13:02 2009
    Info: Elapsed time: 00:00:02