?? uart_mega128isr.lst
字號:
__start:
__text_start:
004E EFCF LDI R28,0xFF
004F E1D0 LDI R29,0x10
0050 BFCD OUT P3D,R28
0051 BFDE OUT P3E,R29
0052 51C0 SUBI R28,0x10
0053 40D0 SBCI R29,0
0054 EA0A LDI R16,0xAA
0055 8308 STD R16,0+Y
0056 2400 CLR R0
0057 E1E0 LDI R30,0x10
0058 E0F1 LDI R31,1
0059 E011 LDI R17,1
005A 39E4 CPI R30,0x94
005B 07F1 CPC R31,R17
005C F011 BEQ 0x005F
005D 9201 ST R0,Z+
005E CFFB RJMP 0x005A
005F 8300 STD R16,0+Z
0060 E8EC LDI R30,0x8C
0061 E0F0 LDI R31,0
0062 E0A0 LDI R26,0
0063 E0B1 LDI R27,1
0064 E010 LDI R17,0
0065 39EC CPI R30,0x9C
0066 07F1 CPC R31,R17
0067 F021 BEQ 0x006C
0068 95C8 LPM
0069 9631 ADIW R30,1
006A 920D ST R0,X+
006B CFF9 RJMP 0x0065
006C 940E00CC CALL _main
_exit:
006E CFFF RJMP _exit
FILE: C:\work\UART_MEGA128\uart2.c
(0001) #include<iom128v.h>
(0002) #include<macros.h>
(0003) #define com0
(0004) #define fosc 4000000 //晶振4MHZ
(0005) #define baud 2400 //波特率
(0006) #define RXC_BUFF_SIZE 64
(0007) #define TXC_BUFF_SIZE 64
(0008) unsigned char RXC_BUFF[RXC_BUFF_SIZE];
(0009) unsigned char TXC_BUFF[TXC_BUFF_SIZE];
(0010) unsigned char RXC_RD;//接受緩沖區讀指針
(0011) unsigned char RXC_WR;//接受緩沖區寫指針
(0012) unsigned char TXC_RD;//發送緩沖區讀指針
(0013) unsigned char TXC_WR;//發送緩沖區寫指針
(0014) #ifdef com0
(0015) void uart0_init(void)
(0016) {
(0017) UCSR0B = 0x00; //disable while setting baud rate
_uart0_init:
006F 2422 CLR R2
0070 B82A OUT P0A,R2
(0018) UCSR0A = 0x00;
0071 B82B OUT P0B,R2
(0019) UCSR0C =(1<<UCSZ01)|(1<<UCSZ00);//8bit+1bit stop
0072 E086 LDI R24,6
0073 93800095 STS R24,0x95
(0020) UBRR0L=(fosc/16/(baud+1))%256;
0075 E688 LDI R24,0x68
0076 B989 OUT P09,R24
(0021) UBRR0H=(fosc/16/(baud+1))/256;
0077 92200090 STS R2,0x90
(0022) UCSR0B =(1<<RXEN0)|(1<<TXEN0)|(1<<RXCIE0);//RXCEN TXCEN RXCIE
0079 E988 LDI R24,0x98
007A B98A OUT P0A,R24
(0023) }
007B 9508 RET
(0024) #else
(0025) void uart1_init(void)
(0026) {
(0027) UCSR1B = 0x00; //disable while setting baud rate
(0028) UCSR1A = 0x00;
(0029) UCSR1C = (1<<UCSZ11)|(1<<UCSZ10);//8bit+1bit stop
(0030) UBRR1L=(fosc/16/(baud+1))%256;
(0031) UBRR1H=(fosc/16/(baud+1))/256;
(0032) UCSR1B =(1<<RXEN1)|(1<<TXEN1)|(1<<RXCIE1);//RXCEN TXCEN RXCIE
(0033) }
(0034) #endif
(0035) void putchar(unsigned char c)
(0036) {
(0037) TXC_BUFF[TXC_WR]=c;
_putchar:
c --> R16
007C E184 LDI R24,0x14
007D E091 LDI R25,1
007E 91E00110 LDS R30,_TXC_WR
0080 27FF CLR R31
0081 0FE8 ADD R30,R24
0082 1FF9 ADC R31,R25
0083 8300 STD R16,0+Z
(0038) if(TXC_WR<(TXC_BUFF_SIZE-1))
0084 91800110 LDS R24,_TXC_WR
0086 338F CPI R24,0x3F
0087 F420 BCC 0x008C
(0039) TXC_WR++;
0088 5F8F SUBI R24,0xFF
0089 93800110 STS R24,_TXC_WR
008B C003 RJMP 0x008F
(0040) else
(0041) TXC_WR=0;
008C 2422 CLR R2
008D 92200110 STS R2,_TXC_WR
(0042) #ifdef com0
(0043) UCSR0B|=(1<<UDRIE0);//開啟UDRE中斷
008F 9A55 SBI P0A,5
(0044) #else
(0045) UCSR1B|=(1<<UDRIE1);
(0046) #endif
(0047) }
0090 9508 RET
(0048) unsigned char getchar(void)
(0049) {
(0050) unsigned temp;
(0051) while(RXC_RD==RXC_WR)
_getchar:
temp --> R16
0091 90200112 LDS R2,_RXC_WR
0093 90300113 LDS R3,_RXC_RD
0095 1432 CP R3,R2
0096 F3D1 BEQ 0x0091
(0052) ;
(0053) temp=RXC_BUFF[RXC_RD];
0097 E584 LDI R24,0x54
0098 E091 LDI R25,1
0099 2DE3 MOV R30,R3
009A 27FF CLR R31
009B 0FE8 ADD R30,R24
009C 1FF9 ADC R31,R25
009D 8100 LDD R16,0+Z
009E 2711 CLR R17
(0054) if(RXC_RD<(RXC_BUFF_SIZE-1))
009F 2D83 MOV R24,R3
00A0 338F CPI R24,0x3F
00A1 F420 BCC 0x00A6
(0055) RXC_RD++;
00A2 5F8F SUBI R24,0xFF
00A3 93800113 STS R24,_RXC_RD
00A5 C003 RJMP 0x00A9
(0056) else
(0057) RXC_RD=0;
00A6 2422 CLR R2
00A7 92200113 STS R2,_RXC_RD
(0058) return temp;
00A9 9508 RET
_puts:
s --> R20
00AA 940E013F CALL push_gset1
00AC 01A8 MOVW R20,R16
(0059) }
(0060) void puts(char *s)
(0061) {
00AD C005 RJMP 0x00B3
(0062) while (*s)
(0063) {
(0064) putchar(*s);
00AE 01FA MOVW R30,R20
00AF 8100 LDD R16,0+Z
00B0 DFCB RCALL _putchar
(0065) s++;
00B1 5F4F SUBI R20,0xFF
00B2 4F5F SBCI R21,0xFF
00B3 01FA MOVW R30,R20
00B4 8020 LDD R2,0+Z
00B5 2022 TST R2
00B6 F7B9 BNE 0x00AE
(0066) }
(0067) putchar(0x0a);
00B7 E00A LDI R16,0xA
00B8 DFC3 RCALL _putchar
(0068) putchar(0x0d);
00B9 E00D LDI R16,0xD
00BA DFC1 RCALL _putchar
(0069) }
00BB 940E0142 CALL pop_gset1
00BD 9508 RET
(0070) void init_devices(void)
(0071) {
(0072) //stop errant interrupts until set up
(0073) CLI(); //disable all interrupts
_init_devices:
00BE 94F8 BCLR 7
(0074) XDIV = 0x00; //xtal divider
00BF 2422 CLR R2
00C0 BE2C OUT P3C,R2
(0075) XMCRA = 0x00; //external memory
00C1 9220006D STS R2,0x6D
(0076) MCUCR = 0x00;
00C3 BE25 OUT P35,R2
(0077) EICRA = 0x00; //extended ext ints
00C4 9220006A STS R2,0x6A
(0078) EICRB = 0x00; //extended ext ints
00C6 BE2A OUT P3A,R2
(0079) EIMSK = 0x00;
00C7 BE29 OUT P39,R2
(0080) TIMSK = 0x00; //timer interrupt sources
00C8 BE27 OUT P37,R2
(0081) ETIMSK = 0x00; //extended timer interrupt sources
00C9 9220007D STS R2,0x7D
(0082) //all peripherals are now initialised
(0083) }
00CB 9508 RET
(0084) void main(void)
(0085) {
(0086) unsigned char i;
(0087) TXC_RD=0;
_main:
i --> R20
00CC 2422 CLR R2
00CD 92200111 STS R2,_TXC_RD
(0088) TXC_WR=0;
00CF 92200110 STS R2,_TXC_WR
(0089) RXC_RD=0;
00D1 92200113 STS R2,_RXC_RD
(0090) RXC_WR=0;
00D3 92200112 STS R2,_RXC_WR
(0091) init_devices();
00D5 DFE8 RCALL _init_devices
(0092) #ifdef com0
(0093) uart0_init();
00D6 DF98 RCALL _uart0_init
(0094) #else
(0095) uart1_init();
(0096) #endif
(0097) SEI();
00D7 9478 BSET 7
(0098) puts("HELLO!");
00D8 E009 LDI R16,0x9
00D9 E011 LDI R17,1
00DA DFCF RCALL _puts
00DB C012 RJMP 0x00EE
(0099) while(1)
(0100) {
(0101) if (getchar()=='t')//按鍵盤t鍵開始測試
00DC DFB4 RCALL _getchar
00DD 3704 CPI R16,0x74
00DE F479 BNE 0x00EE
(0102) {
(0103) puts("test ok!");
00DF E000 LDI R16,0
00E0 E011 LDI R17,1
00E1 DFC8 RCALL _puts
(0104) for (i=0;i<10;i++)
00E2 2744 CLR R20
00E3 C004 RJMP 0x00E8
(0105) {
(0106) putchar(0x30+i);
00E4 2F04 MOV R16,R20
00E5 5D00 SUBI R16,0xD0
00E6 DF95 RCALL _putchar
00E7 9543 INC R20
00E8 304A CPI R20,0xA
00E9 F3D0 BCS 0x00E4
(0107) }
(0108) putchar(0x0a);
00EA E00A LDI R16,0xA
00EB DF90 RCALL _putchar
(0109) putchar(0x0d);
00EC E00D LDI R16,0xD
00ED DF8E RCALL _putchar
00EE CFED RJMP 0x00DC
(0110) }
(0111) }
(0112) }
00EF 9508 RET
_uart0_rx_isr:
00F0 922A ST R2,-Y
00F1 938A ST R24,-Y
00F2 939A ST R25,-Y
00F3 93EA ST R30,-Y
00F4 93FA ST R31,-Y
00F5 B62F IN R2,P3F
00F6 922A ST R2,-Y
(0113) //中斷例程
(0114) #ifdef com0
(0115) #pragma interrupt_handler uart0_rx_isr:iv_USART0_RXC
(0116) void uart0_rx_isr(void)
(0117) {
(0118) RXC_BUFF[RXC_WR]=UDR0;
00F7 E584 LDI R24,0x54
00F8 E091 LDI R25,1
00F9 91E00112 LDS R30,_RXC_WR
00FB 27FF CLR R31
00FC 0FE8 ADD R30,R24
00FD 1FF9 ADC R31,R25
00FE B02C IN R2,P0C
00FF 8220 STD R2,0+Z
(0119) if(RXC_WR<(RXC_BUFF_SIZE-1))
0100 91800112 LDS R24,_RXC_WR
0102 338F CPI R24,0x3F
0103 F420 BCC 0x0108
(0120) RXC_WR++;
0104 5F8F SUBI R24,0xFF
0105 93800112 STS R24,_RXC_WR
0107 C003 RJMP 0x010B
(0121) else
(0122) RXC_WR=0; //uart has received a character in UDR
0108 2422 CLR R2
0109 92200112 STS R2,_RXC_WR
(0123) }
010B 9029 LD R2,Y+
010C BE2F OUT P3F,R2
010D 91F9 LD R31,Y+
010E 91E9 LD R30,Y+
010F 9199 LD R25,Y+
0110 9189 LD R24,Y+
0111 9029 LD R2,Y+
0112 9518 RETI
_uart0_udre_isr:
0113 922A ST R2,-Y
0114 923A ST R3,-Y
0115 938A ST R24,-Y
0116 939A ST R25,-Y
0117 93EA ST R30,-Y
0118 93FA ST R31,-Y
0119 B62F IN R2,P3F
011A 922A ST R2,-Y
(0124) #pragma interrupt_handler uart0_udre_isr:iv_USART0_UDRE
(0125) void uart0_udre_isr(void)
(0126) {
(0127) UDR0=TXC_BUFF[TXC_RD];//character transferred to shift register so UDR is now empty
011B E184 LDI R24,0x14
011C E091 LDI R25,1
011D 91E00111 LDS R30,_TXC_RD
011F 27FF CLR R31
0120 0FE8 ADD R30,R24
0121 1FF9 ADC R31,R25
0122 8020 LDD R2,0+Z
0123 B82C OUT P0C,R2
(0128) if(TXC_RD<(TXC_BUFF_SIZE-1))
0124 91800111 LDS R24,_TXC_RD
0126 338F CPI R24,0x3F
0127 F420 BCC 0x012C
(0129) TXC_RD++;
0128 5F8F SUBI R24,0xFF
0129 93800111 STS R24,_TXC_RD
012B C003 RJMP 0x012F
(0130) else
(0131) TXC_RD=0;
012C 2422 CLR R2
012D 92200111 STS R2,_TXC_RD
(0132) if(TXC_RD==TXC_WR)
012F 90200110 LDS R2,_TXC_WR
0131 90300111 LDS R3,_TXC_RD
0133 1432 CP R3,R2
0134 F409 BNE 0x0136
(0133) UCSR0B&=~(1<<UDRIE0);
0135 9855 CBI P0A,5
(0134) }
FILE: <library>
0136 9029 LD R2,Y+
0137 BE2F OUT P3F,R2
0138 91F9 LD R31,Y+
0139 91E9 LD R30,Y+
013A 9199 LD R25,Y+
013B 9189 LD R24,Y+
013C 9039 LD R3,Y+
013D 9029 LD R2,Y+
013E 9518 RETI
push_gset1:
013F 935A ST R21,-Y
0140 934A ST R20,-Y
0141 9508 RET
pop_gset1:
0142 E0E1 LDI R30,1
pop:
0143 9149 LD R20,Y+
0144 9159 LD R21,Y+
0145 FDE0 SBRC R30,0
0146 9508 RET
0147 9169 LD R22,Y+
0148 9179 LD R23,Y+
0149 FDE1 SBRC R30,1
014A 9508 RET
014B 90A9 LD R10,Y+
014C 90B9 LD R11,Y+
014D FDE2 SBRC R30,2
014E 9508 RET
014F 90C9 LD R12,Y+
0150 90D9 LD R13,Y+
0151 FDE3 SBRC R30,3
0152 9508 RET
0153 90E9 LD R14,Y+
0154 90F9 LD R15,Y+
0155 9508 RET
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