MEMORY
{
   PAGE 0: VECS:     origin = 0080h, length = 0080h
           PRAM:     origin = 1000h, length = 1000h

   PAGE 1: STACK:    origin = 0100h, length = 0400h
           TABLE:	 origin = 0500h, length = 0400h
           EXRAM:    origin = 2000h, length = 2000h
}

/*****************************************************************************/
/* DSP Memory Allocation                                                     */
/*****************************************************************************/

SECTIONS
{
	.cinit		:> PRAM  PAGE 0
	vectors		:> VECS  PAGE 0
    
	init_var	:> PRAM  PAGE 0
   	
	.stack		:> STACK PAGE 1
	.const		:> EXRAM PAGE 1
	.data		:> EXRAM PAGE 1
	.cio		:> EXRAM PAGE 1
	.switch		:> EXRAM PAGE 1

	Init_table	:> TABLE PAGE 1
}