?? conf_tny.lst
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A51 MACRO ASSEMBLER CONF_TNY 04/26/2009 16:07:33 PAGE 1
MACRO ASSEMBLER A51 V8.01
OBJECT MODULE PLACED IN Conf_tny.OBJ
ASSEMBLER INVOKED BY: D:\Program\KeiC51\C51\BIN\A51.EXE Conf_tny.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the RTX-51 TINY Real-Time Operating System Package
4 ; Copyright KEIL ELEKTRONIK GmbH and Keil Software, Inc. 1991-2002
5 ; Version 2.01
6 ;------------------------------------------------------------------------------
7 ; CONF_TNY.A51: This code allows the configuration of the
8 ; RTX-51 TINY Real-Time Operating System
9 ;
10 ; Copy this file to your project folder and add the copy to your uVision2
11 ; project. You can customize several parameters of RTX51 Tiny within this
12 ; configuration file.
13 ;
14 ; If you use command line tools, translate this file with:
15 ;
16 ; Ax51 CONF_TNY.A51
17 ;
18 ; If you use command line tools, link the modified CONF_TNY.OBJ file to
19 ; your application with:
20 ;
21 ; Lx51 <your object file list>, CONF_TNY.OBJ <controls>
22 ;
23 ;------------------------------------------------------------------------------
24 ;
25 ; RTX-51 TINY Hardware-Timer
26 ; ==========================
27 ;
28 ; With the following EQU statements the initialization of the RTX-51 TINY
29 ; Hardware-Timer can be defined (RTX-51 TINY uses the 8051 Timer 0 for
30 ; controlling RTX-51 software timers).
31 ;
32 ; Define the register bank used for the timer interrupt.
0001 33 INT_REGBANK EQU 1 ; default is Registerbank 1
34 ;
35 ; Define Hardware-Timer tick time in 8051 machine cycles.
2710 36 INT_CLOCK EQU 10000 ; default is 10000 cycles
37 ;
38 ; Define Round-Robin Timeout in Hardware-Timer ticks.
0005 39 TIMESHARING EQU 5 ; default is 5 Hardware-Timer ticks.
40 ; ; 0 disables Round-Robin Task Switching
41 ;
42 ; Long User Interrupt Routines: set to 1 if your application contains
43 ; user interrupt functions that may take longer than a hardware timer
44 ; interval for execution.
0000 45 LONG_USR_INTR EQU 0 ; 0 user interrupts execute fast.
46 ; ; 1 user interrupts take long execution times.
47 ;
48 ;
49 ;------------------------------------------------------------------------------
50 ;
51 ; USER CODE FOR 8051 HARDWARE TIMER INTERRUPT
52 ; ===========================================
53 ;
54 ; The following macro defines the code executed on a hardware timer interrupt.
55 ;
56 ; Define instructions executed on a hardware timer interrupt.
57 HW_TIMER_CODE MACRO
58 ; Empty Macro by default
A51 MACRO ASSEMBLER CONF_TNY 04/26/2009 16:07:33 PAGE 2
59 RETI
60 ENDM
61 ;
62 ;
63 ;------------------------------------------------------------------------------
64 ;
65 ; CODE BANKING SUPPORT
66 ; ====================
67 ;
68 ; The following EQU statement controls the code banking support for RTX51 TINY.
69 ;
70 ; Enable or disable code banking support
0000 71 CODE_BANKING EQU 0 ; 0 (default) application uses no code banking
72 ; ; 1 application uses code banking
73 ;
74 ;------------------------------------------------------------------------------
75 ;
76 ; RTX-51 TINY Stack Space
77 ; =======================
78 ;
79 ; The following EQU statements defines the size of the internal RAM used
80 ; for stack area and the minimum free space on the stack. A macro defines
81 ; the code executed when there is there is not enough free stack on the
82 ; CPU stack.
83 ;
84 ; Define the highest RAM address used for CPU stack
007F 85 RAMTOP EQU 07FH ; default is address (256-1)
86 ;
0014 87 FREE_STACK EQU 20 ; default is 20 bytes free space on stack
88 ; ; the value 0 disables stack checking
89 ;
90 STACK_ERROR MACRO
91 CLR EA ; disable interrupts
92 SJMP $ ; endless loop if stack space is exhausted
93 ENDM
94 ;
95 ;
96 ;------------------------------------------------------------------------------
97 ;
98 ; 8051 CPU IDLE CODE
99 ; ==================
100 ;
101 ; Many 8051 devices provide an IDLE MODE that reduces power consumption and
102 ; EMC. The following macro defines the code executed when there is no
103 ; ready task in the system. The code must set the CPU into an IDLE MODE
104 ; that stops instruction execution until an 8051 hardware interrupt occurs.
105 ;
106
107 ; Disable or Enable CPU_IDLE CODE
0001 108 CPU_IDLE_CODE EQU 1 ; 0 CPU_IDLE MACRO is not inserted
109 ; 1 CPU_IDLE MACRO is executed
110
0087 111 PCON DATA 087H ; Power Control SFR on most 8051 devices
112
113 ; Stop CPU execution until hardware interrupt; executed when there is no
114 ; active task in the system.
115 CPU_IDLE MACRO
116 ORL PCON,#1 ; set 8051 CPU to IDLE
117 ENDM
118 ;
119 ;
120 ;------------------------------------------------------------------------------
121 ;----------------- !!! End of User Configuration Part !!! ------------------
122 ;----------------- !!! Do not modify code sections below !!! ------------------
123 ;------------------------------------------------------------------------------
124
A51 MACRO ASSEMBLER CONF_TNY 04/26/2009 16:07:33 PAGE 3
125 ; SFR Symbols
00D0 126 PSW DATA 0D0H
00E0 127 ACC DATA 0E0H
00F0 128 B DATA 0F0H
0081 129 SP DATA 81H
0082 130 DPL DATA 82H
0083 131 DPH DATA 83H
0088 132 TCON DATA 88H
0089 133 TMOD DATA 89H
008A 134 TL0 DATA 8AH
008B 135 TL1 DATA 8BH
008C 136 TH0 DATA 8CH
008D 137 TH1 DATA 8DH
00A8 138 IE DATA 0A8H
139
140 ; TCON
008F 141 TF1 BIT 8FH
008E 142 TR1 BIT 8EH
008D 143 TF0 BIT 8DH
008C 144 TR0 BIT 8CH
008B 145 IE1 BIT 8BH
008A 146 IT1 BIT 8AH
0089 147 IE0 BIT 89H
0088 148 IT0 BIT 88H
149 ; IE
00AF 150 EA BIT 0AFH
00AC 151 ES BIT 0ACH
00AB 152 ET1 BIT 0ABH
00AA 153 EX1 BIT 0AAH
00A9 154 ET0 BIT 0A9H
00A8 155 EX0 BIT 0A8H
156
157 ; Check Configuration Values
158
159
160 NAME ?RTX51_TINY_KERNAL
161
162 PUBLIC ?RTX_CURRENTTASK
163 PUBLIC ?RTX_RAMTOP
164 PUBLIC os_switch_task
165 PUBLIC ?RTX?SET_ISR
166
167 EXTRN NUMBER (?RTX_MAXTASKN) ; max Task Number
168
007F 169 ?RTX_RAMTOP EQU RAMTOP
D8F0 170 ?RTX_CLOCK EQU -INT_CLOCK
171
0008 172 ?RTX_REGISTERBANK EQU INT_REGBANK * 8
---- 173 DSEG AT ?RTX_REGISTERBANK
0008 174 DS 2 ; temporary space
000A 175 ?RTX_SAVEACC: DS 1
REG 176 saveacc EQU R2 ; for access in interrupt service routine
000B 177 ?RTX_SAVEPSW: DS 1
REG 178 savepsw EQU R3 ; for access in interrupt service routine
000C 179 ?RTX_CURRENTTASK: DS 1
REG 180 currenttask EQU R4 ; for access in interrupt service routine
181
182 IF (TIMESHARING <> 0)
000D 183 ?RTX_ROBINTIME: DS 1
REG 184 robintime EQU R5 ; for access in interrupt service routine
185 ENDIF
186
187 IF (CODE_BANKING <> 0)
EXTRN DATA (?B_CURRENTBANK)
EXTRN CODE (?B_RESTORE_BANK)
ENDIF
A51 MACRO ASSEMBLER CONF_TNY 04/26/2009 16:07:33 PAGE 4
191
192
193 ;------------------------------------------------
194 ; Table of Task Entry Pointers
195 ;------------------------------------------------
196 PUBLIC ?RTX_TASKENTRY
197
198 ?RTX?TASKENT?S SEGMENT CODE
---- 199 RSEG ?RTX?TASKENT?S
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