{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 28 17:06:36 2007 " "Info: Processing started: Sat Jul 28 17:06:36 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Hello -c Hello --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Hello -c Hello --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key\[0\] led\[0\] 12.132 ns Longest " "Info: Longest tpd from source pin \"key\[0\]\" to destination pin \"led\[0\]\" is 12.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns key\[0\] 1 PIN PIN_118 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_118; Fanout = 1; PIN Node = 'key\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Hello" "UNKNOWN" "V1" "E:/Hello/db/Hello.quartus_db" { Floorplan "E:/Hello/" "" "" { key[0] } "NODE_NAME" } "" } } { "Hello.bdf" "" { Schematic "E:/Hello/Hello.bdf" { { 128 24 192 144 "key\[0\]" "" } { 256 16 184 272 "key\[1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.242 ns) + CELL(3.036 ns) 12.132 ns led\[0\] 2 PIN PIN_6 0 " "Info: 2: + IC(8.242 ns) + CELL(3.036 ns) = 12.132 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Hello" "UNKNOWN" "V1" "E:/Hello/db/Hello.quartus_db" { Floorplan "E:/Hello/" "" "11.278 ns" { key[0] led[0] } "NODE_NAME" } "" } } { "Hello.bdf" "" { Schematic "E:/Hello/Hello.bdf" { { 128 240 416 144 "led\[0\]" "" } { 256 184 360 272 "led\[1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.890 ns ( 32.06 % ) " "Info: Total cell delay = 3.890 ns ( 32.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.242 ns ( 67.94 % ) " "Info: Total interconnect delay = 8.242 ns ( 67.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Hello" "UNKNOWN" "V1" "E:/Hello/db/Hello.quartus_db" { Floorplan "E:/Hello/" "" "12.132 ns" { key[0] led[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.132 ns" { key[0] key[0]~combout led[0] } { 0.000ns 0.000ns 8.242ns } { 0.000ns 0.854ns 3.036ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 28 17:06:36 2007 " "Info: Processing ended: Sat Jul 28 17:06:36 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}